WM1811A datasheet(157/328 Pages) WOLFSON

157 / 328 page

Production Data

WM1811A

PD, November 2013, Rev 4.1

157

Mono mode operation is available in DSP interface mode. When Mono mode is enabled, the audio

data is transmitted or received starting on either the 1

st (mode B) or 2nd (mode A) rising edge of BCLK

following a rising edge of LRCLK.

PCM operation is supported in DSP interface mode. WM1811A ADC data that is output on the Left

Channel will be read as mono PCM data by the receiving equipment. Mono PCM data received by the

WM1811A will be treated as Left Channel data. This data may be routed to the Left/Right DACs using

the control fields described in the“Digital Mixing” and “Digital Audio Interface Control” sections.

AUDIO DATA FORMATS (TDM MODE)

TDM is supported in master and slave modes. All audio interface data formats support time division

multiplexing (TDM) for ADC and DAC data.

On AIF1, the TDM format is enabled by register control (AIF1ADC_TDM and AIF1DAC_TDM for the

output and input paths respectively). When TDM is enabled on AIF1, the data formats shown in Figure

57 to Figure 61 are always selected, and the WM1811A transmits or receives AIF1 data in one of the

two available timeslots; the ADCDAT1 output is tri-stated when not outputting data.

Two AIF1 time slots are available (Slot 0 and Slot 1), selected by register bits AIF1ADC_TDM_CHAN

and AIF1DAC_TDM_CHAN; these determine the active time slot for the ADC data and the DAC data

respectively.

On AIF2, the TDM format is enabled by register control (AIF2ADC_TDM and AIF2DAC_TDM for the

output and input paths respectively). When TDM is enabled on AIF2, the data formats shown in Figure

57 to Figure 61 are always selected, and the WM1811A transmits or receives AIF2 data in one of the

two available timeslots; the ADCDAT2 output is tri-stated when not outputting data.

Two AIF2 time slots are available (Slot 0 and Slot 1), selected by register bits AIF2ADC_TDM_CHAN

and AIF2DAC_TDM_CHAN; these determine the active time slot for the ADC data and the DAC data

respectively.

When TDM is enabled, the ADCDAT pin will be tri-stated immediately before and immediately after

data transmission, to allow another ADC device to drive this signal line for the remainder of the

sample period. Note that it is important that two ADC devices do not attempt to drive the data pin

simultaneously. A short circuit may occur if the transmission time of the two ADC devices overlap with

each other. See “Audio Interface Timing” for details of the ADCDAT output relative to BCLK signal.

Note that it is possible to ensure a gap exists between transmissions by setting the transmitted word

length to a value higher than the actual length of the data. For example, if 32-bit word length is

selected where only 24-bit data is available, then the WM1811A interface will tri-state after

transmission of the 24-bit data, ensuring a gap after the WM1811A TDM slot.

When TDM is enabled, the BCLK frequency must be high enough to allow data from both time slots to

be transferred. The relative timing of Slot 0 and Slot 1 depends upon the selected data format, as

shown in Figure 57 to Figure 61.

Figure 57 TDM in Right-Justified Mode

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