WM1811A datasheet(160/328 Pages) WOLFSON

160 / 328 page

WM1811A

Production Data

PD, November 2013, Rev 4.1

160

AIF1 - SIGNAL PATH ENABLE

The AIF1 interface supports two input channels and two output channels. Each of the available

channels can be enabled or disabled using the register bits defined in Table 86. These register

controls are illustrated in Figure 66.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R4 (0004h)

Power

Management

(4)

AIF1ADC1L

_ENA

Enable AIF1ADC (Left) output path

0 = Disabled

1 = Enabled

AIF1ADC1R

_ENA

Enable AIF1ADC (Right) output path

0 = Disabled

1 = Enabled

R5 (0005h)

Power

Management

(5)

AIF1DAC1L

_ENA

Enable AIF1DAC (Left) input path

0 = Disabled

1 = Enabled

AIF1DAC1R

_ENA

Enable AIF1DAC (Right) input path

0 = Disabled

1 = Enabled

Table 86 AIF1 Signal Path Enable

AIF1 - BCLK AND LRCLK CONTROL

The BCLK1 frequency is controlled relative to AIF1CLK by the AIF1_BCLK_DIV divider. See “Clocking

and Sample Rates” for details of the AIF1 clock, AIF1CLK.

The LRCLK1 frequency is controlled relative to BCLK1 by the AIF1DAC_RATE divider.

In Master mode, the LRCLK1 output is generated by the WM1811A when any of the AIF1 channels is

enabled. (Note that, when GPIO1 is configured as ADCLRCLK1, then only the AIF1 DAC channels will

cause LRCLK1 to be output.)

In Slave mode, the LRCLK1 output is disabled by default to allow another digital audio interface to

drive this pin. It is also possible to force the LRCLK1 signal to be output, using the

AIF1DAC_LRCLK_DIR or AIF1ADC_LRCLK_DIR register bits, allowing mixed master and slave

modes. (Note that, when GPIO1 is configured as ADCLRCLK1, then only the AIF1DAC_LRCLK_DIR

bit will force the LRCLK1 signal.)

When the GPIO1 pin is configured as ADCLRCLK1, then the ADCLRCLK1 frequency is controlled

relative to BCLK1 by the AIF1ADC_RATE divider. In this case, the ADCLRCLK1 is dedicated to AIF1

output, and the LRCLK1 pin is dedicated to AIF1 input, allowing different sample rates to be supported

in the two paths.

In Master mode, with GPIO1 pin configured as ADCLRCLK1, this output is enabled when any of the

AIF1 ADC channels is enabled. The ADCLRCLK1 signal can also be enabled in Slave mode, using

the AIF1ADC_LRCLK_DIR bit, allowing mixed master and slave modes.

When the GPIO1 pin is not configured as ADCLRCLK1, then the LRCLK1 signal applies to the ADC

and DAC channels, at a rate set by AIF1DAC_RATE.

See “General Purpose Input/Output” for the configuration of GPIO1.Note that, in Ultrasonic (4FS)

mode, the GPIO1 pin must be configured as ADCLRCLK1.

The BCLK1 output can be inverted using the AIF1_BCLK_INV register bit. The LRCLK1 and

ADCLRCLK1 output (when selected) can be inverted using the AIF1DAC_LRCLK_INV and

AIF1ADC_LRCLK_INV register controls respectively.

Note that in Slave mode, when BCLK1 is an input, the AIF1_BCLK_INV register selects the polarity of

the received BCLK1 signal. Under default conditions, DACDAT1 input is captured on the rising edge

of BCLK1, as illustrated in Figure 4. When AIF1_BCLK_INV = 1, DACDAT1 input is captured on the

falling edge of BCLK1.

WM1811A Datasheet(PDF) 160 Page - Wolfson Microelectronics plc

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