WM1811A datasheet(163/328 Pages) WOLFSON

163 / 328 page

Production Data

WM1811A

PD, November 2013, Rev 4.1

163

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R773 (0305h)

AIF1DAC

LRCLK

AIF1DAC_L

RCLK_INV

Right, left and I

2S modes – LRCLK1 polarity

0 = normal LRCLK1 polarity

1 = invert LRCLK1 polarity

Note that AIF1DAC_LRCLK_INV selects the

LRCLK1 polarity in Master mode and in Slave

mode.

DSP Mode – mode A/B select

0 = MSB is available on 2nd BCLK1 rising

edge after LRCLK1 rising edge (mode A)

1 = MSB is available on 1st BCLK1 rising

edge after LRCLK1 rising edge (mode B)

AIF1DAC_L

RCLK_DIR

Allows LRCLK1 to be enabled in Slave mode

0 = Normal

1 = LRCLK1 enabled in Slave mode

10:0

AIF1DAC_R

ATE [10:0]

040h

LRCLK1 Rate

LRCLK1 clock output =

BCLK1 / AIF1DAC_RATE

Integer (LSB = 1)

Valid from 8..2047

Table 87 AIF1 BCLK and LRCLK Control

AIF1 - DIGITAL AUDIO DATA CONTROL

The register bits controlling the audio data format, word length, left/right channel selection and TDM

control for AIF1 are described in Table 88.

When TDM mode is enabled on AIF1, the WM1811A can transmit and receive audio data in Slot 0 or

Slot 1. In this case, the ADCDAT1 output is tri-stated during the unused timeslot, allowing another

device to transmit data on the same pin. See “Signal Timing Requirements” for the associated timing

details.(Note that, when TDM is not enabled on AIF1, the ADCDAT1 output is driven logic ‘0’ during

the unused timeslot.)

In DSP mode, the left channel MSB is available on either the 1

st (mode B) or 2nd (mode A) rising edge

of BCLK following a rising edge of LRCLK (assuming default BCLK polarity).

When the AIF1DAC_LRCLK_INV bit is set in DSP mode, then DSP Mode B is selected for the AIF1

digital input (playback) signal path. When the AIF1DAC_LRCLK_INV bit is not set, then DSP Mode A

is selected.

When the AIF1ADC_LRCLK_INV bit is set in DSP mode, then DSP Mode B is selected for the AIF1

digital output (record) signal path. When the AIF1ADC_LRCLK_INV bit is not set, then DSP Mode A is

selected.

Note that the DSP Mode is selected independently for the input/output paths of each digital audio

interface. Also note that the AIF1ADCLRCLK_INV bits remain valid even when the LRCLK signal is

common for both paths. See Table 87 for details of the AIF1DAC_LRCLK_INV and

AIF1ADC_LRCLK_INV register fields.

A digital gain function is available at the audio interface input path to boost the DAC volume when a

small signal is received on DACDAT1. This is controlled using the AIF1DAC_BOOST register. To

prevent clipping, this function should not be used when the boosted data is expected to be greater

than 0dBFS.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R768 (0300h)

AIF1 Control

(1)

AIF1ADCL_

SRC

AIF1 Left Digital Audio interface source

0 = Left ADC data is output on left channel

1 = Right ADC data is output on left channel

WM1811A Datasheet(PDF) 163 Page - Wolfson Microelectronics plc

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