WM1811A datasheet(167/328 Pages) WOLFSON

167 / 328 page

Production Data

WM1811A

PD, November 2013, Rev 4.1

167

AIF1 - LOOPBACK

The AIF1 interface can provide a Loopback option. When the AIF1_LOOPBACK bit is set, then AIF1

digital audio output is routed to the AIF1 digital audio input. The normal input (DACDAT1) is not used

when AIF1 Loopback is enabled.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R769 (0301h)

AIF1 Control

(2)

AIF1_LOOP

BACK

AIF1 Digital Loopback Function

0 = No loopback

1 = Loopback enabled (ADCDAT1 data output

is directly input to DACDAT1 data input).

Table 92 AIF1 Loopback

AIF1 - DIGITAL PULL-UP AND PULL-DOWN

The WM1811A provides integrated pull-up and pull-down resistors on each of the DACDAT1, LRCLK1

and BCLK1 pins. This provides a flexible capability for interfacing with other devices.

Each of the pull-up and pull-down resistors can be configured independently using the register bits

described in Table 93. Note that if the Pull-up and Pull-down are both enabled for any pin, then the

pull-up and pull-down will be disabled.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R1824

(0720h)

Pull Control

(1)

DACDAT1_PU

DACDAT1 Pull-up enable

0 = Disabled

1 = Enabled

DACDAT1_PD

DACDAT1 Pull-down enable

0 = Disabled

1 = Enabled

DACLRCLK1_

LRCLK1 Pull-up enable

0 = Disabled

1 = Enabled

DACLRCLK1_

LRCLK1 Pull-down enable

0 = Disabled

1 = Enabled

BCLK1_PU

BCLK1 Pull-up enable

0 = Disabled

1 = Enabled

BCLK1_PD

BCLK1 Pull-down enable

0 = Disabled

1 = Enabled

Table 93 AIF1 Digital Pull-Up and Pull-Down Control

AIF2 - MASTER / SLAVE AND TRI-STATE CONTROL

The Digital Audio Interface AIF2 can operate in Master or Slave modes, selected by AIF2_MSTR. In

Master mode, the BCLK2 and LRCLK2 signals are generated by the WM1811A when one or more

AIF2 channels is enabled.

When AIF2_LRCLK_FRC or AIF2_CLK_FRC is set in Master mode, then LRCLK2 is output at all

times, including when none of the AIF2 audio channels is enabled. Note that LRCLK2 is derived from

BCLK2, and either an internal or external BCLK2 signal must be present to generate LRCLK2.

When AIF2_CLK_FRC is set in Master mode, then BCLK2 is output at all times, including when none

of the AIF2 audio channels is enabled.

WM1811A Datasheet(PDF) 167 Page - Wolfson Microelectronics plc

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