WM1811A datasheet(169/328 Pages) WOLFSON

169 / 328 page

Production Data

WM1811A

PD, November 2013, Rev 4.1

169

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

AIF2TXR_E

Enable AIF2DAC (Right) input path

0 = Disabled

1 = Enabled

This bit must be set for AIF2 output of the

AIF2ADC (Left) signal. For AIF3 output only,

this bit can be set to 0.

Table 95 AIF2 Signal Path Enable

AIF2 - BCLK AND LRCLK CONTROL

The BCLK2 frequency is controlled relative to AIF2CLK by the AIF2_BCLK_DIV divider. See “Clocking

and Sample Rates” for details of the AIF2 clock, AIF2CLK.

The LRCLK2 frequency is controlled relative to BCLK2 by the AIF2DAC_RATE divider.Note that the

LRCLK2 signal is shared by the AIF2 input and AIF2 output paths; accordingly, the AIF2 input and

AIF2 output must always operate at the same sample rate.

In Master mode, the LRCLK2 output is generated by the WM1811A when any of the AIF2 channels is

enabled.

In Slave mode, the LRCLK2 output is disabled by default to allow another digital audio interface to

drive this pin. It is also possible to force the LRCLK2 signal to be output, using the

AIF2DAC_LRCLK_DIR register bit, allowing mixed master and slave modes.

The

BCLK2

and

LRCLK2

output

can

inverted

using

the

AIF2_BCLK_INV

and

AIF2DAC_LRCLK_INV register bits respectively.

Note that in Slave mode, when BCLK2 is an input, the AIF2_BCLK_INV register selects the polarity of

the received BCLK2 signal. Under default conditions, DACDAT2 input is captured on the rising edge

of BCLK2, as illustrated in Figure 4. When AIF2_BCLK_INV = 1, DACDAT2 input is captured on the

falling edge of BCLK2.

The AIF2 clock generators are controlled as illustrated in Figure 65.

Figure 65 Audio Interface 2 - BCLK and LRCLK Control

WM1811A Datasheet(PDF) 169 Page - Wolfson Microelectronics plc

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