WM1811A datasheet(171/328 Pages) WOLFSON

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Production Data

WM1811A

PD, November 2013, Rev 4.1

171

AIF2 - DIGITAL AUDIO DATA CONTROL

The register bits controlling the audio data format, word length, left/right channel selection and TDM

control for AIF2 are described in Table 97.

When TDM mode is enabled on AIF2, the WM1811A can transmit and receive audio data in Slot 0 or

Slot 1. In this case, the ADCDAT2 output is tri-stated during the unused timeslot, allowing another

device to transmit data on the same pin. See “Signal Timing Requirements” for the associated timing

details.(Note that, when TDM is not enabled on AIF2, the ADCDAT2 output is driven logic ‘0’ during

the unused timeslot.)

In DSP mode, the left channel MSB is available on either the 1

st (mode B) or 2nd (mode A) rising edge

of BCLK following a rising edge of LRCLK (assuming default BCLK polarity).

When the AIF2DAC_LRCLK_INV bit is set in DSP mode, then DSP Mode B is selected for the AIF2

digital input (playback) signal path. When the AIF2DAC_LRCLK_INV bit is not set, then DSP Mode A

is selected.

When the AIF2ADC_LRCLK_INV bit is set in DSP mode, then DSP Mode B is selected for the AIF2

digital output (record) signal path. When the AIF2ADC_LRCLK_INV bit is not set, then DSP Mode A is

selected.

Note that the DSP Mode is selected independently for the input/output paths of each digital audio

interface. The LRCLK signal is common for both paths so, for typical applications, the

AIF2DAC_LRCLK_INV and AIF2ADC_LRCLK_INV bits should be set to the same value. The

AIF2DAC_LRCLK_INV bit is defined in Table 96.

A digital gain function is available at the audio interface input path to boost the DAC volume when a

small signal is received on DACDAT2. This is controlled using the AIF2DAC_BOOST register. To

prevent clipping, this function should not be used when the boosted data is expected to be greater

than 0dBFS.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R784 (0310h)

AIF2 Control

(1)

AIF2ADCL_

SRC

AIF2 Left Digital Audio interface source

0 = Left ADC data is output on left channel

1 = Right ADC data is output on left channel

AIF2ADCR_

SRC

AIF2 Right Digital Audio interface source

0 = Left ADC data is output on right channel

1 = Right ADC data is output on right channel

AIF2ADC_T

AIF2 transmit (ADC) TDM Enable

0 = Normal ADCDAT2 operation

1 = TDM enabled on ADCDAT2

AIF2ADC_T

DM_CHAN

AIF2 transmit (ADC) TDM Slot Select

0 = Slot 0

1 = Slot 1

6:5

AIF2_WL

[1:0]

AIF2 Digital Audio Interface Word Length

00 = 16 bits

01 = 20 bits

10 = 24 bits

11 = 32 bits

Note - 8-bit modes can be selected using the

“Companding” control bits.

4:3

AIF2_FMT

[1:0]

AIF2 Digital Audio Interface Format

00 = Right justified

01 = Left justified

10 = I

2S Format

11 = DSP Mode

R785 (0311h)

AIF2 Control

(2)

AIF2DACL_

SRC

AIF2 Left Receive Data Source Select

0 = Left DAC receives left interface data

1 = Left DAC receives right interface data

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