WM1811A datasheet(181/328 Pages) WOLFSON

181 / 328 page

Production Data

WM1811A

PD, November 2013, Rev 4.1

181

Note that the bandwidth of the digital audio mixing paths will be determined by the sample rate of

whichever AIF is selected as the SYSCLK source. When using only one audio interface, the active

interface should be selected as the SYSCLK source. For best audio performance when using AIF1

and AIF2 simultaneously, the SYSCLK source must select the AIF with the highest sample rate

(AIFn_SR).

The AIFnCLK / fs ratio is the ratio of AIFnCLK to the AIFn sample rate, where ‘n’ identifies the

applicable audio interface AIF1 or AIF2. The AIF clocking ratio and sample rate are set by the

AIFnCLK_RATE and AIFn_SR register fields, defined in Table 109 and Table 111.

Note that, in the case of mixed input/output path sample rates (supported on AIF1 only), then

AIFnCLK_RATE and AIFn_SR are set according to the higher of the two sample rates.

The clocking configuration for AIF1CLK, AIF2CLK andSYSCLKis illustrated in Figure 67.The

SYSCLK_SRC register is defined in Table 112.

The WM1811A provides integrated pull-up and pull-down resistors on the MCLK1 and MCLK2 pins.

This provides a flexible capability for interfacing with other devices. This is configured as described in

Table 112. Note that if the Pull-up and Pull-down are both enabled for any pin, then the pull-up and

pull-down will be disabled.

MCLK2

MCLK1

FLL2

AIF1CLK_SRC

AIF2CLK_SRC

FLL1

SYSCLK_SRC

AIF1CLK

SYSCLK

AIF2CLK

AIF1CLK_ENA

AIF1CLK_DIV

f/N

AIF2CLK_ENA

AIF2CLK_DIV

f/N

Figure 67 Audio Interface Clock Control

AIF1CLK ENABLE

The AIF1CLK_SRC register is used to select the AIF1CLK source. The source may be MCLK1,

MCLK2, FLL1 or FLL2. If either of the Frequency Locked Loops is selected as the source, then the

FLL(s) must be enabled and configured as described later.

The AIF1CLK clock may be adjusted by the AIF1CLK_DIV divider, which provides a divide-by-two

option. The selected source may also be inverted by setting the AIF1CLK_INV bit.

The maximum AIF1CLK frequency is specified in the “Electrical Characteristics” section. Note that,

when AIF1CLK_DIV = 1, the maximum frequency limit applies to the divided-down AIF1CLK

frequency.

The AIF1CLK is enabled by the register bit AIF1CLK_ENA. This bit should be set to 0 when

reconfiguring the clock sources. It is not recommended to change AIF1CLK_SRC while the

AIF1CLK_ENA bit is set.

WM1811A Datasheet(PDF) 181 Page - Wolfson Microelectronics plc

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