WM1811A datasheet(178/328 Pages) WOLFSON

178 / 328 page

WM1811A

Production Data

PD, November 2013, Rev 4.1

178

AIF3 - DIGITAL AUDIO DATA CONTROL

The register bits controlling the AIF3Mono PCM interface are described in Table 105.

Note that these registers control the AIF3 Mono PCM interface only; they are not applicable to the

ADCDAT3 and DACDAT3 signal paths when these pins are selected as alternate inputs to the AIF1 or

AIF2 interfaces.

The audio data format for AIF3 is set the same as AIF2; this is controlled using the AIF2_FMT

In DSP mode, the AIF3 Mono channel MSB is available on either the 1

st (mode B) or 2nd (mode A)

rising edge of BCLK following a rising edge of LRCLK. The applicable DSP mode is selected using the

AIF3_LRCLK_INV bit, as described in Table 104.

In Left justified, Right justified and I2S modes, the AIF3 Mono interface data is transmitted and

received in the Left channel data bits of the ADCDAT3 and DACDAT3 channels.

A digital gain function is available at the audio interface input path to boost the DAC volume when a

small signal is received on DACDAT3. This is controlled using the AIF3DAC_BOOST register. To

prevent clipping, this function should not be used when the boosted data is expected to be greater

than 0dBFS.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R800 (0320h)

AIF3 Control

(1)

6:5

AIF3_WL

[1:0]

AIF3 Digital Audio Interface Word Length

00 = 16 bits

01 = 20 bits

10 = 24 bits

11 = 32 bits

Note - 8-bit modes can be selected using the

“Companding” control bits.

Note that this controls the AIF3 Mono PCM

interface path only; it does not affect AIF3

inputs/outputs routed to AIF1 or AIF2.

R801 (0321h)

AIF3 Control

(2)

11:10

AIF3DAC_B

OOST [1:0]

AIF3 Input Path Boost

00 = 0dB

01 = +6dB (input must not exceed -6dBFS)

10 = +12dB (input must not exceed -12dBFS)

11 = +18dB (input must not exceed -18dBFS)

Note that this controls the AIF3 Mono PCM

interface path only; it does not affect

DACDAT3 input to AIF1 or AIF2.

R802 (0322h)

AIF3DAC

Data

AIF3DAC_D

AT_INV

AIF3 Receive Data Invert

0 = Not inverted

1 = Inverted

Note that this controls the AIF3 Mono PCM

interface path only; it does not affect

DACDAT3 input to AIF1 or AIF2.

R803 (0323h)

AIF3ADC

Data

AIF3ADC_D

AT_INV

AIF3 Transmit Data Invert

0 = Not inverted

1 = Inverted

Note that this controls the AIF3 Mono PCM

interface path only; it does not affect

ADCDAT3 output from AIF1 or AIF2.

Table 105 AIF3 Digital Audio Data Control

WM1811A Datasheet(PDF) 178 Page - Wolfson Microelectronics plc

WM1811A Datasheet(HTML) 178 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL