HT1620 datasheet(9/17 Pages) HOLTEK

9 / 17 page

HT1620

July 26, 1999

Functional Description

Display memory - RAM structure

The static display RAM is organized into 32´4

bits and stores the display data. The contents of

the RAM are directly mapped to the contents of

the LCD driver. Data in the RAM can be ac-

cessed by the READ, WRITE and READ-MOD

IFY-WRITE commands. The following is a map-

ping from the RAM to the LCD patterns.

Time base and watchdog timer - WDT

The time base generator and WDT share the

same divided (/256) counter. TIMER DIS/EN/CLR,

WDT DIS/EN/CLR and IRQ EN/DIS are inde-

pendent from each other. Once the WDT

time-out occurs, the IRQ pin will stay at a logic

low level until the CLR WDT or the IRQ DIS

command is issued.

Buzzer tone output

A simple tone generator is implemented in the

HT1620. The tone generator can output a pair

of differential driving signals on the BZ and BZ

which are used to generate a single tone.

LCD driver

The HT1620 is a 128 (32´4) pattern LCD driver.

It can be configured as 1/2 or 1/3 bias and 2 or 3

or 4 commons of LCD driver by the S/W configu-

ration. This feature makes the HT1620 suitable

for multiple LCD applications. The LCD driving

clock is derived from the system clock. The value

of the driving clock is always 256Hz even when it

is at a 32.768kHz crystal oscillator frequency. The

LCD corresponding commands are summarized

in the table.

The bold form of100, namely 100, indicates

the command mode ID. If successive commands

have been issued, the command mode ID will be

omitted, except for the first command. The LCD

OFF command turns the LCD display off by dis-

abling the LCD bias generator. The LCD ON

command, on the other hand, turns the LCD

display on by enabling the LCD bias generator.

The BIAS and COM are the LCD panel related

commands. With the use of the LCD related

commands, the HT1620 can be compatible with

most types of LCD panels.

WD T E N / D I S

IR Q E N /D IS

CL R W D T

C l o ck S o u r ce

/ 256

Ti m e B a s e

CL R T i m e r

IR Q

WD T

VD D

TI ME R E N / D I S

Timer and WDT configurations

SE G 0

SE G 1

SE G 2

SE G 3

SE G 3 1

CO M0

CO M1

CO M2

CO M3

D 3

D 2

D 1

D 0

Da t a

A ddr

A ddr es s 6 bi t s

( A 5, A 4, . . . , A 0 )

Da t a 4 b i t s

( D 3, D 2, D 1, D 0)

RAM mapping

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