HT16270 datasheet(8/17 Pages) HOLTEK

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HT16270

April 21, 2000

90%

50%

10%

GN D

W R , R D

Cl o c k

t f

t r

t CL K

- V DD

Figure 1

50%

VA L I D D A T A

50%

WR , R D

Cl o c k

GN D

t su

t h

V DD

- GN D

Figure 2

GN D

50 %

FI R S T

Cl o c k

LA S T

Cl o c k

GN D

WR , R D

Cl o c k

t su 1

t h1

t CS

- V DD

Figure 3

Functional Description

Display memory - RAM structure

The static display RAM is organized into 256´4

bits and stores the display data. The contents of

the RAM are directly mapped to the contents of

the LCD driver. Data in the RAM can be

accessedbytheREAD,WRITEand

READ-MODIFY-WRITE commands. The fol-

lowing is a mapping from the RAM to the LCD

patterns.

Time base and watchdog timer - WDT

The time base generator and WDT share the

same divided (/256) counter. TIMER DIS/EN/CLR,

WDT DIS/EN/CLR and IRQ EN/DIS are inde-

pendent from each other. Once the WDT

time-out occurs, the IRQ pin will remain at

logic low level until the CLR WDT or the IRQ

DIS command is issued.

SE G 0

SE G 1

SE G 2

SE G 3

SE G 6 3

CO M 1 2

CO M 1 3

CO M 1 4

CO M 1 5

A ddr

255

CO M 0

CO M 1

CO M 2

CO M 3

A ddr

252

Da t a 4 B i t s

( D 3 , D 2 , D 1 , D 0 )

A ddr es s 8 B i t s

( A 7 , A 6 , .... , A 0 )

Da t a

RAM mapping

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