Advanced Power

Electronics Corp.

APE8901

BLOCK DIAGRAM

PIN DESCRIPTION

FB

VIN

VCNTL

POK

EN

4

Connecting this pin to an external resistor divider receives the feedback voltage of the

regulator. The output voltage set by the resistor divider is determined by:

Where R1 is connected from VOUT to FB with Kelvin sensing and R2 is connected from FB

to GND. A bypass capacitor may be connected with R1in parallel to improve load transient

response. The recommended R2 and R1 are in the range of 1K~100kΩ.

Main supply input pins for power conversions. The voltage at this pin is monitored for Power-

On Reset purpose.

Power input pin of the control circuitry. Connecting this pin to a +5V (recommended) supply

voltage provides the bias for the control circuitry. The voltage at this pin is monitored for Power-On

Reset purpose.

Power-OK signal output pin. This pin is an open-drain output used to indicate status of

output voltage by sensing FB voltage. This pin is pulled low when the rising FB voltage is not above

the VPOK threshold or the falling FB voltage is below the VPOK threshold, indicating the output is

not OK.

Enable control pin. Pulling and holding this pin below 0.4V shuts down the output. When re-

enabled, the IC undergoes a new soft-start cycle. Left this pin open, this pin is internal pulled up to

VCNTL voltage, enabling the regulator.

-

+

VIN

VOUT

GND

Error

Amp

EN

VCNTL

Soft-Start

And

Control Logic

Power -ON

Reset

Current

Limit

Enable

Thermal

Shutdown

Bandgap

FB

POK

Delay

POK

-

+

UV

0.4V

90%

Vref

N-MOSFET

90Ω