AT90PWM2 datasheet(182/365 Pages) ATMEL

182 / 365 page

182

4317K–AVR–03/2013

AT90PWM2/3/2B/3B

17.2.5

SPI Status Register – SPSR

• Bit 7 – SPIF: SPI Interrupt Flag

When a serial transfer is complete, the SPIF flag is set. An interrupt is generated if SPIE in

SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is

in Master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the

corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the

SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR).

• Bit 6 – WCOL: Write COLlision Flag

The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The

WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set,

and then accessing the SPI Data Register.

• Bit 5..1 – Res: Reserved Bits

These bits are reserved bits in the AT90PWM2/2B/3/3B and will always read as zero.

• Bit 0 – SPI2X: Double SPI Speed Bit

When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI

is in Master mode (see Table 17-4). This means that the minimum SCK period will be two CPU

clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at f

clkio/4

or lower.

The SPI interface on the AT90PWM2/2B/3/3B is also used for program memory and EEPROM

downloading or uploading. See Serial Programming Algorithm296 for serial programming and

verification.

Table 17-4.

Relationship Between SCK and the Oscillator Frequency

SPI2X

SPR1

SPR0

SCK Frequency

clkio/4

clkio/16

clkio/64

clkio/128

clkio/2

clkio/8

clkio/32

clkio/64

Bit

76543210

SPIF

WCOL

–––––

SPI2X

SPSR

Read/Write

RRRRRRR

R/W

Initial Value

00000000

AT90PWM2 Datasheet(PDF) 182 Page - ATMEL Corporation

AT90PWM2 Datasheet(HTML) 182 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL