AT90PWM2 datasheet(248/365 Pages) ATMEL

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248

4317K–AVR–03/2013

AT90PWM2/3/2B/3B

• Bit 3, 2, 1, 0 – MUX3, MUX2, MUX1, MUX0: ADC Channel Selection Bits

These 4 bits determine which analog inputs are connected to the ADC input. The different set-

ting are shown in Table 21-4.

If these bits are changed during a conversion, the change will not take effect until this conversion

is complete (it means while the ADIF bit in ADCSRA register is set).

21.8.2

ADC Control and Status Register A – ADCSRA

• Bit 7 – ADEN: ADC Enable Bit

Set this bit to enable the ADC.

Clear this bit to disable the ADC.

Clearing this bit while a conversion is running will take effect at the end of the conversion.

• Bit 6– ADSC: ADC Start Conversion Bit

Set this bit to start a conversion in single conversion mode or to start the first conversion in free

running mode.

Cleared by hardware when the conversion is complete. Writing this bit to zero has no effect.

The first conversion performs the initialization of the ADC.

• Bit 5 – ADATE: ADC Auto trigger Enable Bit

Set this bit to enable the auto triggering mode of the ADC.

Clear it to return in single conversion mode.

Table 21-4.

ADC Input Channel Selection

MUX3

MUX2

MUX1

MUX0

Description

0000ADC0

0001ADC1

0010ADC2

0011ADC3

0100ADC4

0101ADC5

0110ADC6

0111ADC7

1000ADC8

1001ADC9

1010ADC10

1011AMP0

1100AMP1 (- is ADC8, + is ADC9)

1101Reserved

1110Bandgap

1111GND

Bit

654

ADEN

ADSC

ADATE

ADIF

ADIE

ADPS2

ADPS1

ADPS0

ADCSRA

Read/Write

R/W

Initial Value

AT90PWM2 Datasheet(PDF) 248 Page - ATMEL Corporation

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