HCPL-3760 datasheet(8/13 Pages) HP

8 / 13 page

1-355

Notes:

1. Measured at a point 1.6 mm below seating plane.

2. Current into/out of any single lead.

3. Surge input current duration is 3 ms at 120 Hz pulse repetition rate. Transient input current duration is 10

µs at 120 Hz pulse

repetition rate. Note that maximum input power, PIN, must be observed.

4. Derate linearly above 70

°C free-air temperature at a rate of 4.1 mW/°C. Maximum input power dissipation of 230 mW allows an input

IC junction temperature of 125

°C at an ambient temperature of T

A = 70°C with a typical thermal resistance from junction to ambient

JA1 = 240°C/W. Excessive PIN and TJ may result in IC chip degradation.

5. Derate linearly above 70

°C free-air temperature at a rate of 5.4 mW/°C.

6. Derate linearly above 70

°C free-air temperature at a rate of 3.9 mW/°C. Maximum output power dissipation of 210 mW allows an

output IC junction temperature of 125

°C at an ambient temperature of T

A = 70°C with a typical thermal resistance from junction to

ambient of

JA0 = 265°C/W.

7. Derate linearly above 70

°C free-air temperature at a rate of 0.6 mA/°C.

8. Maximum operating frequency is defined when output waveform Pin 6 obtains only 90% of VCC with RL = 4.7 kΩ, CL = 30 pF using

a 5 V square wave input signal.

9. All typical values are at TA = 25°C, VCC = 5.0 V unless otherwise stated.

10. The tPHL propagation delay is measured from the 2.5 V level of the leading edge of a 5.0 V input pulse (1 µs rise time) to the 1.5 V

level on the leading edge of the output pulse (see Figure 10).

11. The tPLH propagation delay is measured from the 2.5 V level of the trailing edge of a 5.0 V input pulse (1 µs fall time) to the 1.5 V

level on the trailing edge of the output pulse (see Figure 10).

12. Common mode transient immunity in Logic High level is the maximum tolerable (positive) dVCM/dt on the leading edge of the

common mode pulse, VCM, to insure that the output will remain in a Logic High state (i.e., VO > 2.0 V). Common mode transient

immunity in Logic Low level is the maximum tolerable (negative) dVCM/dt on the trailing edge of the common mode pulse signal,

VCM, to insure that the output will remain in a Logic Low state (i.e., VO < 0.8 V). See Figure 11.

13. In applications where dVCM/dt may exceed 50,000 V/µs (such as static discharge), a series resistor, RCC, should be included to

protect the detector IC from destructively high surge currents. The recommended value for RCC is 240 Ω per volt of allowable drop

in VCC (between Pin 8 and VCC) with a minimum value of 240 Ω.

14. Logic low output level at Pin 6 occurs under the conditions of VIN ≥ VTH+ as well as the range of VIN > VTH– once VIN has exceeded

VTH+. Logic high output level at Pin 6 occurs under the conditions of VIN ≤ VTH- as well as the range of VIN < VTH+ once VIN has

decreased below VTH-.

15. AC voltage is instantaneous voltage.

16. Device considered a two terminal device: Pins 1, 2, 3, 4 connected together, and Pins 5, 6, 7, 8 connected together.

17. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage

≥ 3000 V rms for 1 second

(leakage detection current limit, Ii-o ≤ 5 µA).

Figure 1. Typical Input Characteristics, I

vs. V

(AC Voltage is Instantaneous Value).

HCPL-3760 Datasheet(PDF) 8 Page - Agilent(Hewlett-Packard)

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