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HCTL2016 Datasheet(PDF) 4 Page - Agilent(Hewlett-Packard)

Part # HCTL2016
Description  Quadrature Decoder/Counter Interface ICs
PDF  18 Pages
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Manufacturer  HP [Agilent(Hewlett-Packard)]
Direct Link  http://www.home.agilent.com
Logo HP - Agilent(Hewlett-Packard)

HCTL2016 Datasheet(HTML) 4 Page - Agilent(Hewlett-Packard)

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Functional Pin Description
Table 4. Functional Pin Descriptions
Pin
Pin
Symbol
2000/2016 2020
Description
VDD
16
20
Power Supply
VSS
8
10
Ground
CLK
2
2
CLK is a Schmitt-trigger input for the external clock signal.
CHA
7
9
CHA and CHB are Schmitt-trigger inputs which accept the outputs
CHB
6
8
from a quadrature encoded source, such as incremental optical shaft
encoder. Two channels, A and B, nominally 90 degrees out of phase,
are required.
RST
5
7
This active low Schmitt-trigger input clears the internal position
counter and the position latch. It also resets the inhibit logic. RST is
asynchronous with respect to any other input signals.
OE
4
4
This CMOS active low input enables the tri-state output buffers. The
OE and SEL inputs are sampled by the internal inhibit logic on the
falling edge of the clock to control the loading of the internal position
data latch.
SEL
3
3
This CMOS input directly controls which data byte from the position
latch is enabled into the 8-bit tri-state output buffer. As in OE above,
SEL also controls the internal inhibit logic.
SEL
BYTE SELECTED
0
High
1
Low
CNTDCDR
16
A pulse is presented on this LSTTL-compatible output when the
quadrature decoder has detected a state transition.
U/D
5
This LSTTL-compatible output allows the user to determine whether
the IC is counting up or down and is intended to be used with the
CNTDCDR and CNTCAS outputs. The proper signal U (high level) or D
(low level) will be present before the rising edge of the CNTDCDR and
CNTCAS outputs.
CNTCAS
15
A pulse is presented on this LSTTL-compatible output when the
HCTL-2020 internal counter overflows or underflows. The rising edge
on this waveform may be used to trigger an external counter.
D0
1
1
D1
15
19
D2
14
18
D3
13
17
D4
12
14
D5
11
13
D6
10
12
D7
9
11
NC
6
Not connected - this pin should be left floating.
These LSTTL-compatible tri-state outputs form an 8-bit output port
through which the contents of the 12/16-bit position latch may be read in
2 sequential bytes. The high byte, containing bits 8-15, is read first (on the
HCTL-2000, the most significant 4 bits of this byte are set to 0 internally).
The lower byte, bits 0-7, is read second.



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