HCTL2016 datasheet(5/18 Pages) HP

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Switching Characteristics

Table 5. Switching Characteristics Min/Max specifications at VDD = 5.0 ± 5%, TA = -40 to + 85°C.

Symbol Description

Min.

Max.

Units

1tCLK

Clock period

2tCHH

Pulse width, clock high

3tCD[1]

Delay time, rising edge of clock to valid, updated count

information on D0-7

4tODE

Delay time, OE fall to valid data

5tODZ

Delay time, OE rise to Hi-Z state on D0-7

6tSDV

Delay time, SEL valid to stable, selected data byte

(delay to High Byte = delay to Low Byte)

7tCLH

Pulse width, clock low

8tSS[2]

Setup time, SEL before clock fall

9tOS[2]

Setup time, OE before clock fall

tSH[2]

Hold time, SEL after clock fall

tOH[2]

Hold time, OE after clock fall

tRST

Pulse width, RST low

tDCD

Hold time, last position count stable on D0-7 after clock rise

tDSD

Hold time, last data byte stable after next SEL state change

tDOD

Hold time, data byte stable after OE rise

tUDD

Delay time, U/D valid after clock rise

tCHD

Delay time, CNTDCDR or CNTCAS high after clock rise

tCLD

Delay time, CNTDCDR or CNTCAS low after clock fall

tUDH

Hold time, U/D stable after clock rise

tUDCS

Setup time, U/D valid before CNTDCDR or CNTCAS rise

tCLK-45

tUDCH

Hold time, U/D stable after CNTDCDR or CNTCAS rise

tCLK-45

Notes:

1. tCD specification and waveform assume latch not inhibited.

2. tSS, tOS, tSH, tOH only pertain to proper operation of the inhibit logic. In other cases, such as 8 bit read operations, these setup

and hold times do not need to be observed.

Figure 3. Tri-State Output Timing.

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