ATMEGA8 datasheet(45/331 Pages) ATMEL

45 / 331 page

2486AA–AVR–02/2013

ATmega8(L)

Timed Sequences

for Changing the

Configuration of

the Watchdog

Timer

The sequence for changing the Watchdog Timer configuration differs slightly between the safety

levels. Separate procedures are described for each level.

Safety Level 1

(WDTON Fuse

Unprogrammed)

In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit

to 1 without any restriction. A timed sequence is needed when changing the Watchdog Time-out

period or disabling an enabled Watchdog Timer. To disable an enabled Watchdog Timer and/or

changing the Watchdog Time-out, the following procedure must be followed:

In the same operation, write a logic one to WDCE and WDE. A logic one must be written

to WDE regardless of the previous value of the WDE bit

Within the next four clock cycles, in the same operation, write the WDE and WDP bits as

desired, but with the WDCE bit cleared

Safety Level 2

(WDTON Fuse

Programmed)

In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A

timed sequence is needed when changing the Watchdog Time-out period. To change the

Watchdog Time-out, the following procedure must be followed:

In the same operation, write a logical one to WDCE and WDE. Even though the WDE

always is set, the WDE must be written to one to start the timed sequence

Within the next four clock cycles, in the same operation, write the WDP bits as desired, but with

the WDCE bit cleared. The value written to the WDE bit is irrelevant.

Assembly Code Example

WDT_off:

; reset WDT

WDR

; Write logical one to WDCE and WDE

r16, WDTCR

ori

r16, (1<<WDCE)|(1<<WDE)

out

WDTCR, r16

; Turn off WDT

ldi

r16, (0<<WDE)

out

WDTCR, r16

ret

C Code Example

void

WDT_off(void)

{

/* reset WDT */

_WDR();

/* Write logical one to WDCE and WDE */

WDTCR |= (1<<WDCE) | (1<<WDE);

/* Turn off WDT */

WDTCR = 0x00;

}

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