| Electronic Components Datasheet Search |
|
P0040 Datasheet(PDF) 22 Page - List of Unclassifed Manufacturers |
|
|
|||||||||||||||||||||||||||||
P0040 Datasheet(HTML) 22 Page - List of Unclassifed Manufacturers |
|
22 / 25 page ![]() Demonstration 20 4.4 4.4 Demo Operation This section describes the procedures of running the demonstration FPGA Configuration Demonstration Setup, File Locations, and Instructions Transceiver Loopback Test Demo: Project directory: sfp_hsmb_s4gx_pcie_xcvr_loopback_6p25Gbps_restored Bit Stream used: hsmc_loopback.sof SFP HSMC Setup Insert SFP modules with loopback connectors into SFP ports 0-3 on the SFP HSMC board Set SW5 switches on the SFP HSMC all to the “0” position Stratix IV GX FPGA Development Kit Setup Set SW3 switches 1-3 & 5-8 in the “down” position. Set SW3 switch 4 in the “up” position Set SW4 switches 1,2,4 in the “up” position and switches 3,5,6,8 in the “down” position Set the rotary switch (SW2) to the 0 position Power on the Stratix IV GX FPGA Development Board and download the SOF file (hsmc_loopback.sof) Press and release CPU reset button located on the host board to initiate the test Press and release PB0, enabling comma detect Press and release PB1 enabling channel bonding Press and release PB2, start transmitting PRBS data LED0, LED1, and LED2 should be ON and LED3 should be OFF. Remove one of the SFP modules or one side of a connector so that the loopback will fail. A Failure is indicated on the Stratix IV GX FPGA Dev Kit when LED3 turns ON To reset the board test system, press and release the CPU reset button on the host board Press and release PB1 and PB2 at the same time creates an error in the transmitter data stream, where LED3 should be ON Press and release, the CPU reset button on the host board and verify the results LVDS Loopback Test Demo: Project directory: sfp_hsmb_s4gx_pcie_lvds_loopback_restored Bit Stream used: hsmc_loopback.sof SFP HSMC Setup Insert SFP modules with loopback connectors into SFP ports 4-7 on the SFP HSMC board Set SW4 switches on the SFP HSMC all to the “1” position Stratix IV GX FPGA Development Kit Setup Set SW3 switches 1-4 & 6-8 in the “down” position. Set SW3 switch 5 in the “up” position Set SW4 switches 1,2,4 in the “up” position and switches 3,5,6,8 in the “down” position |
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |