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W185 Datasheet(PDF) 3 Page - Cypress Semiconductor |
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W185 Datasheet(HTML) 3 Page - Cypress Semiconductor |
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3 / 8 page ![]() W185 3 Overview The W185 products are one series of devices in the Cypress PREMIS family. The PREMIS family incorporates the latest advances in PLL spread spectrum frequency synthesizer tech- niques. By frequency modulating the output with a low-fre- quency carrier, peak EMI is greatly reduced. Use of this tech- nology allows systems to pass increasingly difficult EMI testing without resorting to costly shielding or redesign. In a system, not only is EMI reduced in the various clock lines, but also in all signals which are synchronized to the clock. Therefore, the benefits of using this technology increase with the number of address and data lines in the system. The Sim- plified Block Diagram shows a simple implementation. Functional Description The W185 uses a Phase-Locked Loop (PLL) to frequency modulate an input clock. The result is an output clock whose frequency is slowly swept over a narrow band near the input signal. The basic circuit topology is shown in Figure 1. The input reference signal is divided by Q and fed to the phase detector. A signal from the VCO is divided by P and fed back to the phase detector also. The PLL will force the frequency of the VCO output signal to change until the divided output signal and the divided reference signal match at the phase detector input. The output frequency is then equal to the ratio of P/Q times the reference frequency. (Note: For the W184 the output frequency is nominally equal to the input frequency.) The unique feature of the Spread Spectrum Frequency Timing Generator is that a modulating waveform is superimposed at the input to the VCO. This causes the VCO output to be slowly swept across a predetermined frequency band. Because the modulating frequency is typically 1000 times slower than the fundamental clock, the spread spectrum pro- cess has little impact on system performance. Frequency Selection With SSFTG In Spread Spectrum Frequency Timing Generation, EMI re- duction depends on the shape, modulation percentage, and frequency of the modulating waveform. While the shape and frequency of the modulating waveform are fixed for a given frequency, the modulation percentage may be varied. Using frequency select bits (FS1:2 pins), the frequency range can be set. Spreading percentage may be selected as either 1.25% or 3.75% (see Table 1). A larger spreading percentage improves EMI reduction. How- ever, large spread percentages may either exceed system maximum frequency ratings or lower the average frequency to a point where performance is affected. For these reasons, spreading percentage options are provided. Freq. Phase Modulating VCO Post CLKOUT Detector Charge Pump Waveform Dividers Divider Feedback Divider PLL GND VDD Σ Q P Clock Input Reference Input (EMI suppressed) Figure 1. Functional Block Diagram |
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