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GMS30C2116 Datasheet(PDF) 77 Page - Hynix Semiconductor

Part # GMS30C2116
Description  USERS MANUAL
PDF  322 Pages
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Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

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INSTRUCTION SET
3-13
3.4 Logical Instructions
The result of a bitwise logical AND, AND not (ANDN), OR or exclusive OR (XOR) of the
source or immediate operand and the destination operand is placed in the destination
register and the Z flag is set or cleared accordingly. At ANDN, the source operand is used
inverted (itself remaining unchanged).
All operands and the result are interpreted as bit-strings of 32 bits each.
Format
Notation
Operation
RR
AND
Rd, Rs
Rd := Rd and Rs;
-- logical AND
Z := Rd = 0;
RR
ANDN
Rd, Rs
Rd := Rd and not Rs;
-- logical AND with source
Z := Rd = 0;
used inverted
RR
OR
Rd, Rs
Rd := Rd or Rs;
-- logical OR
Z := Rd = 0;
RR
XOR
Rd, Rs
Rd := Rd xor Rs;
-- logical exclusive OR
Z := Rd = 0;
Rimm
ANDNI
Rd, imm
Rd := Rd and not imm;
-- logical AND with imm
Z := Rd = 0;
used inverted
Rimm
ORI
Rd, imm
Rd := Rd or imm;
-- logical OR
Z := Rd = 0;
Rimm
XORI
Rd, imm
Rd := Rd xor imm;
-- logical exclusive OR
Z := Rd = 0;
Note: ANDN and ANDNI are the instructions complementary to OR and ORI: Where OR
and ORI set bits, ANDN and ANDNI clear bits at bit positions with a "one" bit in the
source or immediate operand, thus obviating the need for an inverted mask in most cases.
Register
L0 : $0F0CFFFF
L1 : $FFFF0000
Instruction
AND
L0, L1
; L0 = L0 and L1 = $0F0C0000
ANDN
L0, L1
; L0 = L0 and not L1 = $0000FFFF
OR
L0, L1
; L0 = L0 or L1 = $FFFFFFFF
XOR
L0, L1
; L0 = L0 xor L1 = $F0F3FFFF
ANDNI L0, $1234
; L0 = L0 and not imm = $0F0CEDCB
ORI
L0, $1234
; L0 = L0 or imm = $0F0CFFFF
XORI
L0, $1234
; L0 = L0 xor imm = $0F0CEDCB



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