GMS30C2116 datasheet(27/322 Pages) HYNIX

27 / 322 page

ARCHITECTURE

1-7

1.2 Global Register Set

The architecture provides 32 global registers of 32 bit each. These are:

Program Counter PC

Status Register SR

Floating-point Exception Register FER

G3..G15

General purpose registers

G16..G17

Reserved

G18

Stack Pointer SP

G19

Upper stack Bound UB

G20

Bus Control Register BCR (see section 6. Bus Interface)

G21

Timer Prescaler Register TPR (see section 5. Timer)

G22

Timer Compare Register TCR (see section 5. Timer)

G23

Timer Register TR (see section 5. Timer)

G24

Watchdog Compare Register WCR (see section 6. Bus Interface)

G25

Input Status Register ISR (see section 6. Bus Interface)

G26

Function Control Register FCR (see section 6. Bus Interface)

G27

Memory Control Register MCR (see section 6. Bus Interface)

G28..G31

Reserved

Registers G0..G15 can be addressed directly by the register code (0..15) of an instruction.

Registers G18..G27 can be addressed only by a MOV or MOVI instruction with the high

global flag H set to 1.

(Example)

MOVI

G2, 0x20

; G2 := 0x20 (set H flag)

MOV

G3, G19

; G3 := G19 (G19 (UB) is copied to G3)

GMS30C2116 Datasheet(PDF) 27 Page - Hynix Semiconductor

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