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HDM8515 Datasheet(PDF) 36 Page - Hynix Semiconductor |
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HDM8515 Datasheet(HTML) 36 Page - Hynix Semiconductor |
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36 / 75 page  36 3.9 DiSEqC Interface The DiSEqC system is a communication bus between satellite receivers and satellite peripheral equipment, using only the existing coaxial cable. 1.1 DiSEqC mode According to the value of DiSEqC_mode of 0x31 register, DiSEqC mode can be changed 0: 22KHz tone off 1: 22KHz tone on 2: Burst mode - on for 12.5ms =’0’ 3: Burst mode - modulated 1:2 for 12.5ms =’1’ 4: Modulated with bytes from DiSEqC instruction 1.2 DiSEqC instruction Up to eight instruction data bytes are loaded into a bank of registers(0x29 -0x30). I2C automatic register address incrementing is turn on. The number of bytes in the DiSEqC instruction must be defined in the DiSEqC_length of 0x31 register. When the DiSEqC instruction data bytes have been loaded, set DiSEqC_mode of 0x31 register. At the same time, program DiSEqC_length of 0x31 register. The instruction data is modulated onto 22KHz signal and output from the DISEQC pin. |
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