HDM8513 datasheet(27/67 Pages) HYNIX

27 / 67 page

3.6 Reed Solomon Decoder

The serial output from the Viterbi is provided to the Word Sync circuits which searches for the eight

bit frame sync word which occurs every 204 bytes. By detecting the polarity of the sync word, this

module can correct polarity reversals in the data provided by the Viterbi decoder.

Byte serial data is provided to the convolutional deinterleaver, which reorders the received symbols.

This process causes errors, which typically occur in bursts from the Viterbi decoder, tobe

distributed randomly over many blocks. This deinterleaved data is then provided to the Reed

Solomon decoder which can reduce an error rate of 2 x10

-4 from the Viterbi decoder to less than 1

in 10

-10. The Reed Solomon decoder accepts input data in blocks of 204 bytes and produces error

corrected blocks of 188 bytes. Maximum 8 bytes per a RS block can be corrected in RS decoder.

Reedsolomon block includes on-chip BER calculator at the output of Viterbi to monitor signal

quality or estimate the SNR of incoming signal. The calculated value can be read by accessing two

read registers via utility bus such as I2C. It represents the number of errors among 2

20 data bits.

The next process is descrambling, not to be confused with the descrambling which is part of

conditional access. The purpose of scrambling the transmitted data and performing the inverse in

the receiver is to insure that the spectrum of the transmitted waveform is always evenly distributed

without significant discrete spectral lines. Without the scrambling/descrambling process, a

transmitted sequence of all ones or all zeroes would result in strong spectral components and

could interfere with other signals in the same satellite transponder.

The final process is data regulation. Viterbi Data and Viterbi Clock occur irregularly according to

the code rate. Data clock regulation makes it possible to interface with external common interface

devices. To make external bus interface more flexible, interface mode such as parallel or serial can

be selected by mode selection register.

Parameter

Regulate_data_clk

Bit 5 of 14H register

Serial_valid

Bit 6 of 14H register

Mode_serial

Bit 0 of 18H register

l NORMAL INTERFACE MODE (parallel/serial)

If regulate_data_clk is reset, both parallel interface and serial interface work in normal

operation which is same as HDM8513 regardless of serial_valid bit. Parallel interface or serial

interface can be alternated by modifying mode_serial bit (Refer to Figure 9 and Figure 10)

l REGULATED INTERFACE MODE (parallel)

If regulate_data_clk is set,all interfaces are from internal FIFO designed to regulate irregular

interface signals. Data clock cycle is a little bit faster than the average of cycle of irregular data

clock, so meaningless data can be output in invalid data period. (Refer to Figure 11)

l REGULATED INTERFACE MODE (serial)

If mode_serial bit is set in the regulate interface mode, regulate interface mode is enabled for

serial interface. Regular serial interface mode has two modes for more flexibi lity. The mode

selection is controlled by serial_valid bit. If serial_valid is reset, DATA_STB signal alternates

when every valid bit is out (mode1). While serial_valid is set, DATA_STB signal sustains high

when valid bit is out (mode2). (Refer to Figure 12 and Figure 13)

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