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HMS81020TL Datasheet(PDF) 39 Page - Hynix Semiconductor |
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HMS81020TL Datasheet(HTML) 39 Page - Hynix Semiconductor |
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39 / 77 page ![]() HMS81004E/08E/16E/24E/32E 36 JUNE 2001 Ver 1.00 11. BASIC INTERVAL TIMER The HMS81004E/08E/16E/24E/32E has one 8-bit Basic Interval Timer that is free-run and can not stop. Block dia- gram is shown in Figure 11-1 . The Basic Interval Timer generates the time base for Standby release time, watchdog timer counting, and etc. It also provides a Basic interval timer interrupt (IFBIT). As the count overflow from FFH to 00H, this overflow causes the interrupt to be generated. -8bit binary up-counter -Use the bit output of prescaler as input to secure the oscil- lation stabilization time after power-on -Secures the oscillation stabilization time in standby mode (stop mode) release -Contents of B.I.T can be read -Provides the clock for watch dog timer The Basic Interval Timer is controlled by the clock control register (CKCTLR) shown in Figure 11-2 . If bit3(BTCL) of CKCTLR is set to “1”, B.I.T is cleared, and then, after one machine cycle, BTCL becomes “0”, and B.I.T starts counting. BTCL is set to ``0`` in reset state. The input clock of B.I.T can be selected from the prescaler within a range of 2us to 256us by clock input selection bits (BTS2~BTS0). (at fex = 4MHz). In reset state, or power on reset, BTS2=“1”, BTS1= “1”, BTS0= “1” to secure the longest oscillation stabilization time. B.I.T can generate the wide range of basic interval time interrupt request (IF- BIT) by selecting prescaler output. By reading of the Basic Interval Timer Register (BITR), we can read counter value of B.I.T. Because B.I.T can be cleared or read, the spending time up to maximum 65.5ms can be available. B.I.T is read-only register. If B.I.T reg- ister is written, then CKCTLR register with same address is written. Figure 11-1 Block diagram of Basic Interval Timer MUX Basic Interval Timer Interrupt Select Input clock 3 Basic Interval Timer source clock 8-bit up-counter BTS[2:0] BTCL ÷8 ÷1024 ÷512 ÷256 ÷128 ÷64 ÷32 ÷16 To Watchdog timer (WDTR) CKCTLR clear overflow Internal bus line clock control register [0C7H] IFBIT Read BITR |
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