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ICS1892 Datasheet(PDF) 139 Page - Integrated Circuit Systems |
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ICS1892 Datasheet(HTML) 139 Page - Integrated Circuit Systems |
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139 / 148 page ![]() Chapter 10 DC and AC Operating Conditions ICS1892, Rev. D, 2/26/01 February 26, 2001 139 ICS1892 © 2000-2001, Integrated Circuit Systems, Inc. All rights reserved. 10.5.16 Reset: Power-On Reset Table 10-23 lists the significant time periods for the power-on reset (which consists of timings of signals on the VDD and TXCLK pins). Figure 10-16 shows the timing diagram for the time periods. Figure 10-16. Power-On Reset Timing Diagram Table 10-23. Power-On Reset Timing Time Period Parameter Conditions Min. Typ. Max. Units t1 VDD ≥ 4.75 V to Reset Complete – 109 – 200 ms TXCLK Valid VDD 4.75 V t1 |
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