ICS1892 datasheet(19/148 Pages) ICST

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Chapter 5

Operating Modes Overview

ICS1892, Rev. D, 2/26/01

February 26, 2001

ICS1892

5.1.2

Specific Reset Operations

This section discusses the following specific ways that the ICS1892 can be reset:

• Hardware reset (using the RESET* pin)

• Power-on reset (applying power to the ICS1892)

• Software reset (using Control Register bit 0.15)

Note:

At the completion of a reset (either hardware, power-on, or software), the ICS1892 sets all

registers to their default values.

5.1.2.1

Hardware Reset

Entering Hardware Reset

Holding the active-low RESET* pin low for a minimum of five REF_IN clock cycles initiates a hardware

reset (that is, the ICS1892 enters the reset state). During reset, the ICS1892 executes the steps listed in

Section 5.1.1.1, “Entering Reset”.

Exiting Hardware Reset

After the signal on the RESET* pin transitions from a low to a high state, the ICS1892 completes in 640 ns

(that is, in 16 REF_IN clocks) steps 1 through 5, listed in Section 5.1.1.2, “Exiting Reset”. After the first five

steps are completed, the Serial Management Port is ready for normal operations, but this action does not

signify the end of the reset cycle. The reset cycle completes when the transmit clock (TXCLK) and receive

clock (RXCLK) are available, which is typically 53 ms after the RESET* pin goes high. [For details on this

transition, see Section 10.5.17, “Reset: Hardware Reset and Power-Down”.]

Note:

The MAC/Repeater Interface is not available for use until the TXCLK and RXCLK are valid.

The Control Register bit 0.15 does not represent the status of a hardware reset. It is a self-clearing bit

that is used to initiate a software reset.

5.1.2.2

Power-On Reset

Entering Power-On Reset

When power is applied to the ICS1892, it waits until the potential between VDD and VSS achieves a

minimum voltage of 4.5 VDC before entering reset and executing the steps listed in Section 5.1.1.1,

“Entering Reset”. After entering reset from a power-on condition, the ICS1892 remains in reset for

approximately 20

µs. (For details on this transition, see Section 10.5.16, “Reset: Power-On Reset”.)

Exiting Power-On Reset

The ICS1892 automatically exits reset and performs the same steps as for a hardware reset. (See Section

5.1.1.2, “Exiting Reset”.)

Note:

The only difference between a hardware reset and a power-on reset is that during a power-on

reset, the ICS1892 isolates the RESET* input pin. All other functionality is the same. As with a

hardware reset, the Control Register bit 0.15 does not represent the status of a power-on reset.

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