ICS1893 datasheet(133/152 Pages) ICST

133 / 152 page

Chapter 10

DC and AC Operating Conditions

ICS1893 Rev C 6/6/00

June, 2000

133

ICS1893 - Release

10.5.7

MII Management Interface Timing

Table 10-14 lists the significant time periods for the MII Management Interface timing (which consists of

timings of signals on the MDC and MDIO pins). Figure 10-8 shows the timing diagram for the time periods.

† The ICS1893 is tested at 25 MHz (a 40-ns period) with a 50-pF load. Designs must account for all board loading of

MDC.

Figure 10-8.

MII Management Interface Timing Diagram

Table 10-14.

MII Management Interface Timing

Time

Period

Parameter

Conditions

Min.

Typ.

Max.

Units

MDC Minimum High Time

–

160

–

MDC Minimum Low Time

–

160

–

MDC Period

–

400†

†

–

MDC Rise Time to MDIO Valid

–

300

MDIO Setup Time to MDC

–

MDIO Hold Time after MDC

–

MDC

MDIO

(Output)

MDC

MDIO

(Input)

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