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ICS1893 Datasheet(PDF) 129 Page - Integrated Circuit Systems |
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ICS1893 Datasheet(HTML) 129 Page - Integrated Circuit Systems |
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129 / 152 page ![]() Chapter 10 DC and AC Operating Conditions ICS1893 Rev C 6/6/00 June, 2000 129 ICS1893 - Release Copyright © 2000, Integrated Circuit Systems, Inc. All rights reserved. 10.5.3 Timing for Receive Clock (RXCLK) Pins Table 10-10 lists the significant time periods for signals on the Receive Clock (RXCLK) pins for the various interfaces. Figure 10-4 shows the timing diagram for the time periods. Figure 10-4. Receive Clock Timing Diagram Table 10-10. MII Receive Clock Timing Time Period Parameter Conditions Min. Typ. Max. Units t1 RXCLK Duty Cycle – 35 50 65 % t2a RXCLK Period 100M MII (100Base-TX) – 40 – ns t2b RXCLK Period 10M MII (10Base-T) – 400 – ns t2c RXCLK Period 100M Symbol Interface (100Base-TX) – 40 – ns t2d RXCLK Period 10M Serial Interface (10Base-T) – 100 – ns RXCLK t1 t2 |
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