ICS9112-18

Zero Delay, Low Skew Buffer

MDS 9112-18 F

2

Revision 050400

Printed 11/15/00

Integrated Circuit Systems, Inc.• 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com

Pin Descriptions

Key: I = Input; O = output; P = power supply connection.

Pin Assignment

ICS9112-18

External Components

The ICS9112-18 requires a minimum number of external components for proper operation. Decoupling

capacitors of 0.1µF should be connected between VDD and GND on pins 4 and 5, and VDD and GND

on pins 13 and 12, as close to the device as possible. A series termination resistor of 33

Ω may be used close

to the pin for each clock output to reduce reflections.

16

15

14

13

16 pin narrow (150 mil) SOIC

12

11

10

9

1

2

3

4

5

6

7

8

CLKA1

GND

FBIN

CLKIN

VDD

S2

CLKB1

CLKB2

VDD

GND

CLKB3

S1

CLKB4

CLKA4

CLKA3

CLKA2

S2

S1

Clocks A1-A4

Clocks B1-B4

Internal Generation

PLL Status

0

0

Tri-state (high impedance)

Tri-state (high impedance)

None

On

0

1

Running

Tri-state (high impedance)

PLL

On

1

0

Running

Running

Buffer Only (no zero delay)

Off

1

1

Running

Running

PLL

On

Feedback From

CLKA1:A4

CLKB1:B4

Bank A

CLKIN

CLKIN/2

Bank B

2XCLKIN

CLKIN

Number

Name

Type

Description

1

CLKIN

I

CLocK INput. Connect to input clock source.

2, 3, 14, 15

CLKA1:4

O

CLocK A bank of four outputs.

4, 13

VDD

P

Power supply. Connect both pins to same voltage (either 3.3V or 5V).

5, 12

GND

P

Connect to ground.

6, 7, 10, 11

CLKB1:4

O

CLocK B bank of four outputs. These are low skew divide by two of bank A.

8

S2

I

Select input #2. Selects mode for outputs per table above.

9

S1

I

Select input #1. Selects mode for outputs per table above.

16

FBIN

I

FeedBack INput. Determines outputs per Feedback Configuration Table above.

Output Clock Mode Select Table

Feedback Configuration Table