4

ICS9248- 131

Byte0: Functionality and Frequency Select Register (default = 0)

Serial Configuration Command Bitmap

Note 1. Default at Power-up will be for latched logic inputs to define frequency. Bits 4, 5, 6 are default to 001, and if bit

3 is written to a 1 to use Bits 6:4, then these should be defined to desired frequency at same write cycle.

Note: PWD = Power-Up Default

Byte 1: CPU,Active/Inactive Register

(1 = enable, 0 = disable)

Notes:

1. Inactive means outputs are held LOW and are disabled

from switching.

Notes:

1. Inactive means outputs are held LOW and are disabled

from switching.

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Byte 2: PCIActive/Inactive Register

(1 = enable, 0 = disable)

Bit

PWD

Bit7 Bit2

0,0

0,1

1,0

1,1

Bit6 Bit5 Bit4

CPU Clock

PCI

AGP

111

100

33.33

66.67

110

95.25

31.75

63.50

101

83.3

33.30

66.60

100

97

32.33

64.66

011

91.5

30.50

61.00

010

96.22

32.07

64.15

001

66.67

33.33

66.67

000

60

30.00

60.00

Bit 1

Bit 0

1 - Tristate all outputs

0 - Frequency is selected by hardware select, Latched inputs

1 - Frequency is selected by Bit 6:4 (above)

0 to -0.5 Down Spread Spectrum Modulation

+/- 0.375% Center Spread Spectrum Modulation

0

0

0 - Normal

1 - Spread Spectrum Enabled

0 - Running

Description

Note1

001

Bit 3

Bit 6:4

Bit 7,2

0,0

Spread Spectrum Method

+/- 0.25% Center Spread Spectrum Modulation

+/- 0.15% Center Spread Spectrum Modulation

0