2

ICS9248-97

Pin Descriptions

The ICS9248-97 is a main clock synthesizer chip for Pentium II based systems using Rambus Interface DRAMs. This chip

provides all the clocks required for such a system when used with a Direct Rambus Clock Generator(DRCG) chip such as the

ICS9212-01.

Spread Spectrum may be enabled by driving the SPREAD# pin active. Spread spectrum typically reduces system EMI by 8dB

to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-97

employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature

variations.

The CPU/2 clocks are inputs to the DRCG.

General Description

Pin number

Pin name

Type

Description

1, 7, 13, 19, 25, 31 GND

PWR

Ground pins

2

REF0

OUT

14.318MHz reference clock outputs at 3.3V

REF1

OUT

14.318MHz reference clock outputs at 3.3V

SEL24_48

IN

Logic input to select 24 or 48MHz for pin 26 output

4, 10, 16, 23,

28, 35

VDD

PWR

Power pins 3.3V

5

X1

IN

XTAL_IN 14.318MHz crystal input

6

X2

OUT

XTAL_OUT Crystal output

PCICLK_F

OUT

Free running PCI clock at 3.3V. Synchronous to CPU clocks. Not

affected by the PCI_STOP# input.

FS0

IN

Logic - input for frequency selection

PCICLK0

OUT

PCI clock output at 3.3V. Synchronous to CPU clocks.

FS1

IN

Logic - input for frequency selection

PCICLK1

OUT

PCI clock output at 3.3V. Synchronous to CPU clocks.

FS2

IN

Logic - input for frequency selection

PCICLK2

OUT

PCI clock output at 3.3V. Synchronous to CPU clocks.

FS3

IN

Logic - input for frequency selection

22, 21, 20, 18, 17,

15, 14

PCICLK (9:3)

OUT

PCI clock outputs at 3.3V. Synchronous to CPU clocks.

24

PD#

IN

This asynchronous input powers down the chip when drive

active(Low). The internal PLLs are disabled and all the output clocks

are held at a Low state.

26

24_48MHz

OUT

24 or 48MHz output selectable by

SEL24_48# (0=48MHz 1=24MHz)

48MHz

OUT/IN

Fixed 48MHz clock output. 3.3V

FS4

IN

Logic - input for frequency selection

29

SCLK

IN

Clock input of I

2

C input

30

SDATA

IN

Data input for I

2

C serial input.

32, 33, 34

3V66 (2:0)

OUT

3.3V clock outputs. These outputs are stopped when CPU_STOP#

is driven active..

36

GNDLCPU

PWR

Ground pin for the CPUCLKs

37, 38, 40

CPUCLK (2:0)

OUT

Host bus clock output at 2.5V.

39

VDDLCPU

PWR

Power pin for the CPUCLKs. 2.5V

41

GNDLCPU/2

PWR

Ground pin for the CPU/2 clocks.

42

CPU/2

OUT

2.5V clock outputs at 1/2 CPU frequency.

43

VDDLCPU/2

PWR

Power pin for the CPU/2 clocks. 2.5V

45

GNDLAPIC

PWR

Ground pin for the IOAPIC outputs.

44, 46, 47

IOAPIC (2:0)

OUT

IOAPIC clocks at 2.5V. Synchronous with CPUCLKs.

48

VDDLAPIC

PWR

Power pin for the IOAPIC outputs. 2.5V.

27

12

3

8

9

11