2

ICS9250-11

Pin Descriptions

Pin number

Pin name

Type

Description

1, 52, 53

GNDLAPIC

PWR

Ground pin for the IOAPIC outputs.

2, 3, 50, 51, 54, 55

IOAPIC (0:5)

OUT

2.5V clock outputs running divide synchronous with the CPU

(Host bus) clock frequency. The default APIC is running at ¼ of

CPUCLK frequency.

When FREQ_APIC is strapped low, the APIC is running at fixed

16.67 MHz.

If CPU = 133 MHz, APIC = CPU/8

If CPU = 100 MHz, APIC = CPU/6

4, 49, 56

VDDLAPIC

PWR

Power pin for the IOAPIC outputs. 2.5V.

5, 11

VDDREF

PWR

Power pin for REF clocks

6

X1

IN

XTAL_IN 14.318MHz crystal input

7

X2

OUT

XTAL_OUT Crystal output

REF0

OUT

3.3V 14.318 MHz clock output. APIC clock strapping option for

fixed 16.67 MHz APIC clock outputs.

FREQ_APIC#

OUT

If FREQ_APIC# = 0, APIC Clock = 16.67 MHz

If FREQ_APIC# = Open, APIC Clock = CPU/4

REF1

OUT

3.3V 14.318MHz clock output.

TEST#

OUT

TEST# is sampled low (external with 10k pulldown). All clock

outputs are Tri-State.

12, 19

VDD66

PWR

power pin for the 3V66 clocks.

13, 14, 17, 18

3V66[0:3]

OUT

66MHz outputs at 3.3V. These outputs are stopped when

CPU_STOP# is driven active..

8, 15, 16, 23, 24

GND

PWR

Ground pin for 3V outputs.

21, 22

3V33MHz

OUT

3.3V Fixed 33MHz clock output.

25

VDDCOR

PWR

3.3V power for PLL core.

26

GND48

PWR

Ground pin for the 48MHz output

27

48MHz

OUT

Fixed 48MHz clock output. 3.3V

28

VDD48

PWR

Power pin for the 48MHz output.

29

SEL 133/100#

IN

This selects the frequency for the CPU and CPU/2 outputs. High =

133MHz, Low=100MHz

30, 31

SEL[0:1]

IN

Function select pins. See truth table for details.

32

SPREAD#

IN

Enables spread spectrum when active(Low). modulates all the CPU,

PCI, IOAPIC, 3V66 and CPU/2 clocks. Does not affect the REF and

48MHz clocks. 0.5% down spread modulation.

33

VDDLCPU/2

PWR

Power pin for the CPU/2 clocks. 2.5V

34, 35

CPU/2[0:1]

OUT

2.5V clock outputs at 1/2 CPU frequency. 66MHz or50MHz

depending on the state of the SEL 133/100# input pin.

36

GNDLCPU/2

PWR

Ground pin for the CPU/2 clocks.

37, 44, 45

GNDLCPU

PWR

Ground pin for the CPUCLKs

38, 39, 42, 43, 46,

47

CPUCLK[0:5]

OUT

Host bus clock output at 2.5V. 133MHz or 100MHz depending on

the state of the SEL 133/100MHz.

40, 41, 48

VDDLCPU

PWR

Power pin for the CPUCLKs. 2.5V

9

10