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ICS9250-28 Datasheet(PDF) 4 Page - Integrated Circuit Systems

Part # ICS9250-28
Description  Frequency Generator & Integrated Buffers for Celeron & PII/III?
PDF  17 Pages
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Manufacturer  ICST [Integrated Circuit Systems]
Direct Link  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS9250-28 Datasheet(HTML) 4 Page - Integrated Circuit Systems

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ICS9250-28
Byte 3: ICS Reserved Functionality and frequency select register (Default as noted in PWD)
2
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Truth Table
Note 1: For system operation, the BSEL lines of the CPU will program FS0, FS2 for the appropriate CPU speed, always
with SDRAM = 100MHz. After BIOS verifies the SDRAM is PC133 speed, then bit 0 can be written from the
default 0 to 1 to change the SDRAM output frequency from 100MHz to 133MHz. This will only change if the
CPU is at the 133MHz FSB speed as shown in this table. The CPU, 3V66, PCI, and IOAPIC clocks will be glitch
free during this transition, and only SDRAM will change.
Note 2: "ICS RESERVED BITS" must be writtern as "0".
Note3: Undefined bits can be written either as "1 or 0"
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