5

ICS9250-28

Byte 0: Control Register

(1 = enable, 0 = disable)

Byte 1: Control Register

(1 = enable, 0 = disable)

t

i

B#

n

i

Pe

m

a

ND

W

Pn

o

i

t

p

i

r

c

s

e

D

7

t

i

B-

D

I

d

e

v

r

e

s

e

R0

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

6

t

i

B-

D

I

d

e

v

r

e

s

e

R0

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

5

t

i

B-

D

I

d

e

v

r

e

s

e

R0

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

4

t

i

B-

D

I

d

e

v

r

e

s

e

R1

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

3

t

i

B-

m

u

r

t

c

e

p

S

d

a

e

r

p

S

)

f

f

O

=

0

/

n

O

=

1

(

1)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

2

t

i

B7

21

z

H

M

8

41

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

1

t

i

B6

20

z

H

M

8

41

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

0

t

i

B-

D

I

d

e

v

r

e

s

e

R0

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

t

i

B#

n

i

Pe

m

a

ND

W

Pn

o

i

t

p

i

r

c

s

e

D

7

t

i

B8

37

M

A

R

D

S1

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

6

t

i

B1

46

M

A

R

D

S1

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

5

t

i

B2

45

M

A

R

D

S1

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

4

t

i

B5

44

M

A

R

D

S1

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

3

t

i

B6

43

M

A

R

D

S1

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

2

t

i

B7

42

M

A

R

D

S1

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

1

t

i

B0

51

M

A

R

D

S1

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

0

t

i

B1

50

M

A

R

D

S1

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

Note: Reserved ID bits must be written as "0"

Byte 2: Control Register

(1 = enable, 0 = disable)

Notes:

1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be

configured at power-on and are not expected to be configured during the normal modes of operation.

2. PWD = Power on Default

3. Undefined bit can be wirtten with either a "1" or "0".

t

i

B#

n

i

Pe

m

a

ND

W

Pn

o

i

t

p

i

r

c

s

e

D

7

t

i

B2

1)

P

G

A

(

2

-

6

6

V

31

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

6

t

i

B9

22

1

M

A

R

D

S1

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

5

t

i

B2

31

1

M

A

R

D

S1

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

4

t

i

B3

30

1

M

A

R

D

S1

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

3

t

i

B6

39

M

A

R

D

S1

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

2

t

i

B7

38

M

A

R

D

S1

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

1

t

i

B6

11

K

L

C

I

C

P1

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

0

t

i

B-

d

e

v

r

e

s

e

R0

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(