AD9802 datasheet(11/20 Pages) AD

11 / 20 page

AD9802

–11–

REV. 0

droop specifications needed. A capacitor value of 0.01

µF will

result in a droop of less than 10 LSB across one video line, and

requires only a CLAMP pulse of 1

µs to charge up. A larger

capacitor may be used to reduce droop, but then a longer

CLAMP pulse may be necessary.

SHA

ADCIN

CML

SHABYP

1V p-p

+3V

ADCMODE

AD9802

VRT

500

CIN

CLAMP

AD8047

500

SD210

VRB

Figure 26. Video Clamp Circuit

1.0

600

100

200

300

400

500

0.5

700

800

900

1023

Figure 27. Direct ADC-Mode Typical INL

1.0

600

100

200

300

400

500

0.5

700

800

900

1023

Figure 28. Direct ADC-Mode Typical DNL

FREQUENCY – MHz

–100

9.0

Figure 29. Direct ADC Mode Typical FFT; FIN = 3.58 MHz,

FS = 18 MHz

Figures 27–29 show the typical linearity and distortion perfor-

mance of the AD9802 in direct ADC mode.

Digitally Programmable Gain Control

The AD9802’s PGA is controlled by an analog input voltage of

0.3 V to 2.7 V. In some applications, digital gain control is

preferable. Figure 30 shows a circuit using Analog Devices’

AD8402 Digital Potentiometer to generate the PGA control

voltage. The AD8402 functions as two individual potentiom-

eters, with a serial digital interface to program the position of

each wiper over 256 positions. The device will operate with 3 V

or 5 V supplies, and features a power-down mode and a reset

function.

To keep external components to a minimum, the ends of the

“potentiometers” can be tied to ground and +3 V. One pot is

used for the coarse gain adjust, PGACONT1, with steps of

about 0.2 dB/LSB. The other pot is used for fine gain control,

PGACONT2, and is capable of around 0.01 dB steps if all

eight bits are used. The two outputs should be filtered with

µF or larger capacitors to minimize noise into the PGACONT

pins of the AD9802.

AD8402-10

+3V

SDI CLK

SHDN CS

0.1 F1 F

+3V

PGACONT1

1 F

PGACONT2

Figure 30. Digital Control of PGA

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