MK1574

Frame Rate Communications PLL

MDS 1574-01 D

1

Revision 011999

Printed 11/15/00

MicroClock Division of ICS • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel•(408)295-9818fax

I C R O

• Packaged in 16 pin narrow (150 mil) SOIC

• Exact multiplications stored in the device eliminate

the need for external dividers

• Accepts 8 kHz input clock

• Output clock rates include T1, E1, T2, E2

• 3.0V to 5.5V operation

• Available in commercial (0 to +70 C) or industrial

(-40 to +85 C) temperature ranges

• For jitter attenuation, use the MK2049

The MK1574-01 is a Phase-Locked Loop (PLL)

based clock synthesizer, which accepts an 8 kHz

clock input as a reference, and generates many

popular communications frequencies. All outputs

are frequency locked together and to the input.

This allows for the generation of locked clocks to

the 8 kHz backplane clock, simplifying clock

generation and distribution in communications

systems.

MicroClock can customize this device for any

other different frequencies.

Block Diagram

Description

Features

Input

Buffer

VDD

GND

PLL

Clock

Synthesis

and

Control

Circuitry

8kHz

Input Clock

Output

Buffer

Output

Buffer

CLK1

2

2

Output

Buffer

CLK2

FS0-3

CLK3

4

Output

Buffer

8kHz

(recovered)

CAP1

CAP2