MK2703

PLL Audio Clock Synthesizer

MDS 2703 C

3

Revision 062700

Printed 11/16/00

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com

I C R O

Parameter

Conditions

Minimum

Typical

Maximum

Units

ABSOLUTE MAXIMUM RATINGS (note 1)

ABSOLUTE MAXIMUM RATINGS (note 1)

Supply voltage, VDD

Referenced to GND

7

V

Inputs and Clock Outputs

Referenced to GND

-0.5

VDD+0.5

V

Ambient Operating Temperature

MK2703S

0

70

°C

MK2703SI

-40

85

°C

Soldering Temperature

Max of 10 seconds

260

°C

Storage temperature

-65

150

°C

DC CHARACTERISTICS (VDD = 3.3 V unless noted)

DC CHARACTERISTICS (VDD = 3.3 V unless noted)

Operating Voltage, VDD

3.13

5.50

V

Input High Voltage, VIH, X1 pin only

(VDD/2)+1

VDD/2

V

Input Low Voltage, VIL, X1 pin only

VDD/2

(VDD/2)-1

V

Input High Voltage, VIH

2

V

Input Low Voltage, VIL

0.8

V

Output High Voltage, VOH

IOH=-12mA

2.4

V

Output Low Voltage, VOL

IOL=12mA

0.4

V

Output High Voltage, VOH, CMOS level

IOH=-4mA

VDD-0.4

V

Operating Supply Current, IDD

No Load

25

mA

Short Circuit Current

Each output

±50

mA

Input Capacitance

S1, S0

5

pF

Frequency synthesis error

All clocks

0

ppm

AC CHARACTERISTICS (VDD = 3.3 V unless noted)

AC CHARACTERISTICS (VDD = 3.3 V unless noted)

Input Crystal Frequency

27.00

MHz

Input Crystal Accuracy

±30

ppm

Output Clock Rise Time

0.8 to 2.0V

1.5

ns

Output Clock Fall Time

2.0 to 0.8V

1.5

ns

Output Clock Duty Cycle

At VDD/2

40

60

%

Maximum Absolute Jitter, short term

±190

ps

Electrical Specifications

Notes:

1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged

exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.

External Components

The MK2703 requires a minimum number of external components for proper operation. For a crystal input,

one load capacitor should be connected from each of the X1 and X2 pins to ground. The value (in pF) of

each crystal load capacitor should equal (CL-16)•2, where CL is the crystal’s load (correlation) capacitance

in pF. The input crystal must be connected as close to the chip as possible. The input crystal should be a

parallel resonant, fundamental, AT cut 27 MHz. For a clock input, connect to X1 and leave X2

unconnected. Decoupling capacitors of 0.01µF should be connected between VDD and GND on pins 2

and 3, as close to the MK2703 as possible. A series termination resistor of 33

Ω may be used for the clock

output.