OBSOLETE

AD9624

REV. 0

–4–

Layout Considerations

As with all wide bandwidth components, printed circuit layout

is critical to obtain best dynamic performance with the AD9624.

The ground plane in the area of the amplifier and its associated

components should cover as much of the component side of the

board as possible (or first interior layer of a multilayer surface

mount board).

The ground plane should be removed in the area of the inputs

supply trace should be decoupled close to the package with a

0.1

µF ceramic capacitor, plus a 6.8 µF tantalum nearby.

All lead lengths for input, output, and feedback resistor should

be kept as short as possible. All gain setting resistors should be

chosen for low values of parasitic capacitance and inductance,

i.e., microwave resistors and/or carbon resistors.

Stripline techniques should be used for lead lengths in excess of

one inch. Sockets should be avoided if at all possible because of

their high series inductance. If sockets are necessary, individual

pin sockets such as AMP p/n 6-330808-3 should be used. These

contribute far less stray reactance than molded socket

assemblies.

An evaluation board is available from Analog Devices for a

nominal charge.

Under certain conditions, it can be used to further enhance set-

tling time performance.

µF) connects to the internal high im-

pedance nodes of the amplifier. Using this capacitor will reduce

the large signal (4 V) step output settling time by 3 ns to 5 ns

for 0.05% or greater accuracy. For settling accuracy less than

0.05% or for smaller step sizes, its effect will be less apparent.

Under heavy slew conditions, this capacitor forces the internal

signal (initial step) amplitude to be controlled by the “on”

(slewed) transistor, preventing its complement from completely

turning off. This allows for faster settling time of these (internal)

nodes and also the output.

In the frequency domain, total (high frequency) distortion will

APPLICATIONS

The AD9624 is a voltage feedback amplifier and is well suited

for such applications as active filters, and log amplifiers. The

device’s wide bandwidth (190 MHz), phase margin (65

°), low

noise current (2.5 pA /

higher performance capabilities to these applications over previ-

ous voltage feedback designs.

Its settling time of 15 ns to 0.01% and 8 ns to 0.1%, and its low

harmonic distortion make it a good for choice for ADC signal

amplification. With superb linearity at relatively high signal fre-

quencies, it is an ideal driver for ADCs up to 14 bits.

R

F

C

F

C

I

V

OUT

Figure 1. Transimpedance

Configuration

R

G

2

3

4

7

6

0.1

µF

0.1

µF

1

8

6.8

µF

V

IN

6.8

µF

+V

S

–V

S

C

F

V

OUT

R

F

500

Ω

A

R

F

R

G

C

Figure 3. Noninverting Gain Connection

Diagram

2

3

4

7

6

0.1

µF

0.1

µF

1

8

6.8

µF

R

F

R

G

R

G

V

IN

6.8

µF

+V

S

–V

S

C

F

V

OUT

R

F

500

Ω

A

–R

F

R

G

C

Figure 2. Inverting Gain Connection

Diagram