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IDT6116LA55DB Datasheet(PDF) 6 Page - Integrated Device Technology

Part # IDT6116LA55DB
Description  CMOS STATIC RAM 16K (2K x 8 BIT)
PDF  11 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT6116LA55DB Datasheet(HTML) 6 Page - Integrated Device Technology

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IDT6116SA/LA
CMOS Static RAM 2K (16K x 8-Bit)
Military, Commercial, and In dustrial Temperature Ranges
AC Electrical Characteristics (VCC = 5V ± 10%, All Temperature Ranges) (continued)
NOTES:
1. 0°C to +70°C temperature range only.
2. –55°C to +125°C temperature range only.
3. This parameter guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
AC Electrical Characteristics (VCC = 5V ± 10%, All Temperature Ranges)
Symbol
Parameter
6116SA15(1)
6116SA20
6116LA20
6116SA25
6116LA25
6116SA35
6116LA35
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Read Cycle
tRC
Read Cycle Time
15
____
20
____
25
____
35
____
ns
tAA
Address Access Time
____
15
____
19
____
25
____
35
ns
tACS
Chip Select Access Time
____
15
____
20
____
25
____
35
ns
tCLZ(3)
Chip Select to Output in Low-Z
5
____
5
____
5
____
5
____
ns
tOE
Output Enable to Output Valid
____
10
____
10
____
13
____
20
ns
tOLZ(3)
Output Enable to Output in Low-Z
0
____
0
____
5
____
5
____
ns
tCHZ(3)
Chip Dese lect to Output in High-Z
____
10
____
11
____
12
____
15
ns
tOHZ(3)
Output Disable to Output in High-Z
____
8
____
8
____
10
____
13
ns
tOH
Output Hold from Address Change
5
____
5
____
5
____
5
____
ns
tPU(3)
Chip Select to Power Up Time
0
____
0
____
0
____
0
____
ns
tPD(3)
Chip Desele ct to Power Down Time
____
15
____
20
____
25
____
35
ns
3089 tbl 12
Symbol
Parameter
6116SA45
6116LA45
6116SA55(2)
6116LA55(2)
6116SA70(2)
6116LA70(2)
6116SA90(2)
6116LA90(2)
6116SA120(2)
6116LA120(2)
6116SA150(2)
6116LA150(2)
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Read Cycle
tRC
Read Cycle Time
45
____
55
____
70
____
90
____
120
____
150
____
ns
tAA
Address Access Time
____
45
____
55
____
70
____
90
____
120
____
150
ns
tACS
Chip Select Access Time
____
45
____
50
____
65
____
90
____
120
____
150
ns
tCLZ(3)
Chip Select to Output in Low-Z
5
____
5
____
5
____
5
____
5
____
5
____
ns
tOE
Output Enable to Output Valid
____
25
____
40
____
50
____
60
____
80
____
100
ns
tOLZ(3)
Output Enable to Output in Low-Z
5
____
5
____
5
____
5
____
5
____
5
____
ns
tCHZ(3)
Chip Dese lect to Output in High-Z
____
20
____
30
____
35
____
40
____
40
____
40
ns
tOHZ(3)
Output Disable to Output in High-Z
____
15
____
30
____
35
____
40
____
40
____
40
ns
tOH
Output Hold from Address Change
5
____
5
____
5
____
5
____
5
____
5
____
ns
3089 tbl 13



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