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IDT6116LA55DB Datasheet(PDF) 8 Page - Integrated Device Technology

Part # IDT6116LA55DB
Description  CMOS STATIC RAM 16K (2K x 8 BIT)
PDF  11 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT6116LA55DB Datasheet(HTML) 8 Page - Integrated Device Technology

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IDT6116SA/LA
CMOS Static RAM 2K (16K x 8-Bit)
Military, Commercial, and In dustrial Temperature Ranges
AC Electrical Characteristics (VCC = 5V ± 10%, All Temperature Ranges)
NOTES:
1. 0°C to +70°C temperature range only.
2. –55°C to +125°C temperature range only.
3. This parameter guaranteed with AC Load (Figure 2) by device characterization, but is not production tested.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operation conditions. Although tDH and tOW values will vary over voltage
and temperature, the actual tDH will always be smaller than the actual tOW.
AC Electrical Characteristics (VCC = 5V ± 10%, All Temperature Ranges) (continued)
6116SA15(1)
6116SA20
6116LA20
6116SA25
6116LA25
6116SA35
6116LA35
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Write Cycle
tWC
Write Cycle Time
15
____
20
____
25
____
35
____
ns
tCW
Chip Select to End-of-Write
13
____
15
____
17
____
25
____
ns
tAW
Address Valid to End-of-Write
14
____
15
____
17
____
25
____
ns
tAS
Address Set-up Time
0
____
0
____
0
____
0
____
ns
tWP
Write Pulse Width
12
____
12
____
15
____
20
____
ns
tWR
Write Recovery Time
0
____
0
____
0
____
0
____
ns
tWHZ(3)
Write to Output in High-Z
____
7
____
8
____
16
____
20
ns
tDW
Data to Write Time Overlap
12
____
12
____
13
____
15
____
ns
tDH(4)
Data Hold from Write Time
0
____
0
____
0
____
0
____
ns
tOW(3,4)
Output Active from End-of-Write
0
____
0
____
0
____
0
____
ns
3089 tbl 14
6116SA45
6116LA45
6116SA55(2)
6116LA55(2)
6116SA70(2)
6116LA70(2)
6116SA90(2)
6116LA90(2)
6116SA120(2)
6116LA120(2)
6116SA150(2)
6116LA150(2)
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Write Cycle
tWC
Write Cycle Time
45
____
55
____
70
____
90
____
120
____
150
____
ns
tCW
Chip Select to End-of-Write
30
____
40
____
40
____
55
____
70
____
90
____
ns
tAW
Address Valid to End-of-Write
30
____
45
____
65
____
80
____
105
____
120
____
ns
tAS
Address Set-up Time
0
____
5
____
15
____
15
____
20
____
20
____
ns
tWP
Write Pulse Width
25
____
40
____
40
____
55
____
70
____
90
____
ns
tWR
Write Recovery Time
0
____
5
____
5
____
5
____
5
____
10
____
ns
tWHZ(3)
Write to Output in High-Z
____
25
____
30
____
35
____
40
____
40
____
40
ns
tDW
Data to Write Time Overlap
20
____
25
____
30
____
30
____
35
____
40
____
ns
tDH(4)
Data Hold from Write Time
0
____
5
____
5
____
5
____
5
____
10
____
ns
tOW(3,4)
Output Active from End-of-Write
0
____
0
____
0
____
0
____
0
____
0
____
ns
3089 tbl 15



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