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Part Number HEX7

Copyright © 2014 ABCircuits. Revised September 2014 Page 3 of 6

POL

Polarity input. If this pin is open or high, the “on” segments will have a high level on the SEG

outputs of the chip. If this pin is low or grounded “on” segments will output as a low on the SEG

pins. This pin is read once at power up and has a built in pull up resistor.

SEGLA, SEGLB, SEGLC, SEGLD, SEGLE, SEGLF, SEGLG

SEGRA, SEGRB, SEGRC, SEGRD, SEGRE, SEGRF, SEGRG

SEGL is the left hand of the two displays.

SEGR is the right hand of the two displays

If the POL pin is open or hi, this SEG outputs will be high when a segment is on.

If the POL pin is low or grounded, the SEG outputs will be low when a segment is on.

These are the seven segment outputs to each individual display An external driver or current

limiting resistor is required for each segment. If you are using only a resistor, it must be sized to

limit source current to 5 mA maximum per pin or sink current to 9 mA per pin.

See also the segment table, and the seven segment translation table.

L1, L2, L4, L8

R1, R2, R4, R8

Parallel input of the data to be displayed. L1-4 is the left digit, R1-4 is the right digit. 1’s are least

significant bit, and 8’s are most significant bit.

VSS

Connect to system ground.

VDD

Connect to supply voltage of 2.4 to 5 volts. A .1 uF decoupling capacitor to ground is

recommended.

NOTES:

Make no connection to the NC pins. Pins 9 and 19 must be left unconnected.

Segment Identification Table