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28F016SA Datasheet(PDF) 34 Page - Intel Corporation |
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28F016SA Datasheet(HTML) 34 Page - Intel Corporation |
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34 / 55 page ![]() 28F016SA E 34 For Extended Status Register Reads Temp Commercial Commercial Comm/Ext Load 30 pF 50 pF 50 pF Versions(5) VCC ± 5% 28F016SA-070(6) Units VCC ± 10% 28F016SA-080(7) 28F016SA-100(7) Sym Parameter Notes Min Max Min Max Min Max tAVEL Address Setup to CE# Going Low 3,4 0 0 0 ns tAVGL Address Setup to OE# Going Low 3,4 0 0 0 ns NOTES: 1. See AC Input/Output Reference Waveforms for timing measurements, Figures 7 and 8. 2. OE# may be delayed up to tELQV–tGLQV after the falling edge of CE# without impact on tELQV. 3. Sampled, not 100% tested. 4. This timing parameter is used to latch the correct BSR data onto the outputs. 5. Device speeds are defined as: 70/80 ns at VCC = 5.0V equivalent to 120 ns at VCC = 3.3V 100 ns at VCC = 5.0V equivalent to 150 ns at VCC = 3.3V 6. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for High Speed Test Configuration. 7. See Standard AC Input/Output Reference Waveforms and AC Testing Load Circuit. |
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