AD5204/AD5206

Rev. C | Page 16 of 20

TEST CIRCUITS

LOGIC

Figure 25. ESD Protection of Digital Pins

A, B, W

Figure 26. ESD Protection of Resistor Terminals

V+

DUT

A

B

W

1LSB = V+/256

Figure 27. Potentiometer Divider Nonlinearity Error Test Circuit (INL, DNL)

DUT

A

B

W

NO CONNECT

Figure 28. Resistor Position Nonlinearity Error

(Rheostat Operation; R-INL, R-DNL)

V+

A

B

W

DUT

V+

Figure 29. Wiper Resistance Test Circuit

V+

A

B

W

~

PSRR (dB) = 20 log

PSS (%/%) =

(

)

Figure 30. Power Supply Sensitivity Test Circuit (PSS, PSRR)

A

OFFSET BIAS

OP279

5V

DUT

W

OFFSET

GND

B

Figure 31. Inverting Programmable Gain Test Circuit

A

OFFSET BIAS

OP279

5V

DUT

W

OFFSET

GND

B

Figure 32. Noninverting Programmable Gain Test Circuit

B

A

2.5V

+15V

DUT

W

–15V

OFFSET

GND

OP42

Figure 33. Gain vs. Frequency Test Circuit

DUT

B

W

0.1V

CODE = 0x00

0.1V

+

–

Figure 34. Incremental On-Resistance Test Circuit