8088 datasheet(14/30 Pages) INTEL

14 / 30 page

8088

The basic difference between the interrupt acknowl-

edge cycle and a read cycle is that the interrupt ac-

knowledge (INTA) signal is asserted in place of the

read (RD) signal and the address bus is floated

(See Figure 9) In the second of two successive INTA

cycles a byte of information is read from the data

bus as supplied by the interrupt system logic (ie

8259A priority interrupt controller) This byte identi-

fies the source (type) of the interrupt It is multiplied

by four and used as a pointer into the interrupt vec-

tor lookup table as described earlier

Bus TimingMedium Complexity

Systems

(See Figure 10)

For medium complexity systems the MNMX pin is

connected to GND and the 8288 bus controller is

added to the system as well as a latch for latching

the system address and a transceiver to allow for

bus loading greater than the 8088 is capable of han-

dling Signals ALE DEN and DTR are generated

by the 8288 instead of the processor in this configu-

ration although their timing remains relatively the

same The 8088 status outputs (S2 S1 and S0) pro-

vide type of cycle information and become 8288 in-

puts

This bus cycle information specifies read

(code data or IO) write (data or IO) interrupt ac-

knowledge or software halt The 8288 thus issues

control signals specifying memory read or write IO

read or write or interrupt acknowledge The 8288

provides two types of write strobes normal and ad-

vanced to be applied as required The normal write

strobes have data valid at the leading edge of write

The advanced write strobes have the same timing

as read strobes and hence data is not valid at the

leading edge of write The transceiver receives the

usual T and OE inputs from the 8288’s DTR and

DEN outputs

The pointer into the interrupt vector table which is

passed during the second INTA cycle can derive

from an 8259A located on either the local bus or the

system bus If the master 8289A priority interrupt

controller is positioned on the local bus a TTL gate

is required to disable the transceiver when reading

from the master 8259A during the interrupt acknowl-

edge sequence and software ‘‘poll’’

The 8088 Compared to the 8086

The 8088 CPU is an 8-bit processor designed

around the 8086 internal structure Most internal

functions of the 8088 are identical to the equivalent

8086 functions The 8088 handles the external bus

the same way the 8086 does with the distinction of

handling only 8 bits at a time Sixteen-bit operands

are fetched or written in two consecutive bus cycles

Both processors will appear identical to the software

engineer with the exception of execution time The

internal register structure is identical and all instruc-

tions have the same end result The differences be-

tween the 8088 and 8086 are outlined below The

engineer who is unfamiliar with the 8086 is referred

to the iAPX 86 88 User’s Manual Chapters 2 and 4

for function description and instruction set informa-

tion Internally there are three differences between

the 8088 and the 8086 All changes are related to

the 8-bit bus interface

The queue length is 4 bytes in the 8088 whereas

the 8086 queue contains 6 bytes or three words

The queue was shortened to prevent overuse of

the bus by the BIU when prefetching instructions

This was required because of the additional time

necessary to fetch instructions 8 bits at a time

To further optimize the queue the prefetching al-

gorithm was changed The 8088 BIU will fetch a

new instruction to load into the queue each time

there is a 1 byte hole (space available) in the

queue The 8086 waits until a 2-byte space is

available

The internal execution time of the instruction set

is affected by the 8-bit interface All 16-bit fetches

and writes fromto memory take an additional

four clock cycles The CPU is also limited by the

speed of instruction fetches This latter problem

only occurs when a series of simple operations

occur When the more sophisticated instructions

of the 8088 are being used the queue has time to

fill and the execution proceeds as fast as the exe-

cution unit will allow

The 8088 and 8086 are completely software com-

patible by virtue of their identical execution units

Software that is system dependent may not be com-

pletely transferable but software that is not system

dependent will operate equally as well on an 8088

and an 8086

The hardware interface of the 8088 contains the ma-

jor differences between the two CPUs The pin as-

signments are nearly identical however with the fol-

lowing functional changes

A8–A15These pins are only address outputs

on the 8088 These address lines are latched in-

ternally and remain valid throughout a bus cycle

in a manner similar to the 8085 upper address

lines

BHE has no meaning on the 8088 and has been

eliminated

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