8088

BUS TIMINGMAXIMUM MODE SYSTEM (USING 8288)

NOTES

231456 – 16

3 Cascade address is valid between first and second INTA cycles

4 Two INTA cycles run back-to-back The 8088 local ADDRDATA bus is floating during both INTA cycles Control for

pointer address is shown for second INTA cycle

5 Signals at 8284 or 8288 are shown for reference only

6 The issuance of the 8288 command and control signals (MRDC MWTC AMWC IORC IOWC AIOWC INTA and

DEN) lags the active high 8288 CEN

7 All timing measurements are made at 15V unless otherwise noted

24