8088

TIMING RESPONSES

Symbol

Parameter

8088

8088-2

Units

Test

Min

Max

Min

Max

Conditions

TCLAV

Address Valid Delay

10

110

10

60

ns

TCLAX

Address Hold Time

10

10

ns

TCLAZ

Address Float Delay

TCLAX

80

TCLAX

50

ns

TLHLL

ALE Width

TCLCHb20

TCLCHb10

ns

TCLLH

ALE Active Delay

80

50

ns

TCHLL

ALE Inactive Delay

85

55

ns

TLLAX

Address Hold Time to

TCHCLb10

TCHCLb10

ns

ALE Inactive

TCLDV

Data Valid Delay

10

110

10

60

ns

TCHDX

Data Hold Time

10

10

ns

TWHDX

Data Hold Time after WR

TCLCHb30

TCLCHb30

ns

TCVCTV

Control Active Delay 1

10

110

10

70

ns

TCHCTV Control Active Delay 2

10

110

10

60

ns

TCVCTX

Control Inactive Delay

10

110

10

70

ns

TAZRL

Address Float to READ

0

0

ns

Active

TCLRL

RD Active Delay

10

165

10

100

ns

TCLRH

RD Inactive Delay

10

150

10

80

ns

TRHAV

RD Inactive to Next

TCLCLb45

TCLCLb40

ns

Address Active

TCLHAV

HLDA Valid Delay

10

160

10

100

ns

TRLRH

RD Width

2TCLCLb75

2TCLCLb50

ns

TWLWH

WR Width

2TCLCLb60

2TCLCLb40

ns

TAVAL

Address Valid to ALE Low

TCLCHb60

TCLCHb40

ns

TOLOH

Output Rise Time

20

20

ns

From 08V to 20V

TOHOL

Output Fall Time

12

12

ns

From 20V to 08V

NOTES

1 Signal at 8284A shown for reference only See 8284A data sheet for the most recent specifications

2 Set up requirement for asynchronous signal only to guarantee recognition at next CLK

3 Applies only to T2 state (8 ns into T3 state)

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