22

ADVANCE INFORMATION

83C196LC, 83C196LD — AUTOMOTIVE

•

I/O port pins. The following port pins do not exist in the 83C196LC and LD: P0.0–P0.1, P1.4–P1.7, P2.3

and P2.5, P5.1 and P5.4–P5.7, P6.2 and P6.3. Software can still read and write the associated Px_REG,

Px_MODE, and Px_DIR registers. Configure the registers for the removed pins as follows:

— Clear the corresponding Px_DIR bits. (Configures pins as complementary outputs.)

— Clear the corresponding Px_MODE bits. (Selects I/O port function.)

— Write either “0” or “1” to the corresponding Px_REG bits. (Effectively ties signals low or high.)

— Do not use the bits associated with the removed port pins for conditional branch instructions. Treat

these bits as reserved.

•

P6.7:4. A value written to any of the upper four bits of P6_REG (bits 4–7) is held in a buffer until the corre-

sponding P6_MODE bit is cleared, at which time the value is loaded into the P6_REG bit. A value read

from a P6_REG bit is the value currently in the register, not the value in the buffer. Therefore, any change

to a P6_REG bit can be read only after the corresponding P6_MODE bit is cleared.

•

Reading reserved memory locations. The 87C196JT and JQ implement a precharged peripheral bus

within the microcontroller that returns a logic one when reserved bits are read. The 83C196LC and LD use

a driven bus within the microcontroller that returns the last value driven on the peripheral data bus when

reserved bits are read.

8.0

83C196LC, 83C196LD ERRATA

There is no known device errata at this time.

9.0 DATASHEET REVISION HISTORY

This datasheet is valid for devices with an “A” at the end of the topside field process order (FPO) number.

Datasheets are changed as new device information becomes available. Verify with your local Intel sales

office that you have the latest version before finalizing a design or ordering devices.