ST78C36 datasheet(3/27 Pages) EXAR

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ST78C36/36A

REV. 5.1.0

ECP/EPP PARALLEL PRINTER PORT WITH 16-BYTE FIFO

PIN DESCRIPTION

NAME

44-PLCC

64-LQFP

TYPE

DESCRIPTION

DATA BUS INTERFACE

A10

Address Select Lines. A10 places the ECP control/status/data ports at

0x400 offset from the -CS decoded address.

I/O

Data bus. Bi-directional data port.

-IOR

Active low AT bus I/O Read strobe.

-IOW

-CS

Chip select (active LOW). A LOW at this pin enables the parallel port /

CPU data transfer operation.

IOCHRDY

I/O Channel ready (internal pull-up / three stated active HIGH). This pin

goes low when the device requires addition clock cycles for read and

write.

-IRQ9

-IRQ7

-IRQ5

Interrupt Request Lines (three stated active low).

AEN

DMA address enable (active HIGH). When this line is HIGH, the DMA

controller has control of the address bus.

DRQ3

DRQ2

DRQ1

Active high AT bus DMA ReQuest for channels 3, 2 and 1 (internal pull-

down three stated active HIGH). A request is generated by bringing a

DRQx line to a HIGH level. A DRQx line is held HIGH until the corre-

sponding DMA acknowledge “DACKx*” line goes LOW.

-DACK3

-DACK2

-DACK1

DMA Acknowledge signals for channels 3, 2 and 1 (internal pull-up /three

stated active low).

Terminal Count (active HIGH). The ST78C36 terminates the DMA channel

when a HIGH pulse is detected.

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