4

Signal Descriptions

Power Output Drivers, Output 0 - Output 7 - The input and

output bits corresponding to Output 0 thru Output 7 are

transmitted and received most significant bit (MSB) first via

the SPI bus. The outputs are provided with current limiting

and voltage sense functions for fault indication and protec-

tion. The nominal load current for these outputs is 500mA,

with current limiting set to a minimum of 1.05A. An on-chip

clamp circuit capable of handling 500mA is provided at each

output for clamping inductive loads.

RESET - Active low reset input. When this input line is low,

the shift register and output latches are configured to turn off

all output drivers. A power on clear function may be imple-

pin must not be left floating.

CE - Active low chip enable. Data is transferred from the shift

register to the outputs on the rising edge of this signal. The

falling edge of CE loads the shift register with the output volt-

age sense bits coming from the output stages. The output

driver for the MISO pin is enabled when this pin is low. CE

must be a logic low prior to the first serial clock (SCK) and

must remain low until after the last (eighth) serial clock cycle.

Alow levelon CE also activates an internal disable circuit

used for unlatching output states that are in a fault mode as

FIGURE 1B.

SPI TIMING DIAGRAM

FIGURE 2. BYTE TIMING DIAGRAM WITH ASYNCHRONOUS RESET

CE

(INPUT)

SCK

(INPUT)

MISO

(OUTPUT)

MOSI

(INPUT)

DRIVER

OUTPUT

HIGH

Z

LAST BIT

TRANSMITTED

D70

D60

D10

D71

D61

D11

OLD

FAULT-INDUCED

TURN-OFF

(9)

(11)

(10)

(3)

(7)

(6)

(5)

(12)

(13)

(1)

(4)

(2)

(8)

NEW

OLD

NEW

FAULTS

RESET

76543210

76543210

RESET

CE

SCK

MOSI

MISO

OUTPUTS

CA3282