6

Output Drivers

The output drivers provide and active low output of 500mA

nominal with current limiting set to 1.05A to allow for high

inrush currents. In addition, each output is provided with a

voltage clamp circuit to limit inductive transients. Each out-

put driver is also monitored by a comparator for an out of

saturation condition. If the output voltage of an ON output

pin exceeds the saturation voltage limit, a fault condition is

assumed and the latch driving this output is reset, turning

the output off. The output comparators, which also provide

diagnostic feedback data to the shift register, contain an

internal pull-down current which will cause the cell to indi-

cate a low output voltage if the output is programmed OFF

and the output pin is open circuited.

CE High to Low Transition

When CE is low the three state MISO pin is enabled. On

the falling edge of CE, diagnostic data from the output volt-

age comparators will be latched into the shift register. If an

output is high, a logic one will be loaded into that bit in the

shift register. If the output is low, a logic zero will be loaded.

During the time that CE is low, data bytes controlling the

output drivers are shifted in at the MOSI pin most signifi-

cant bit (MSB) first. A logic zero on this pin will program the

corresponding output to be ON, and a logic one will turn it

OFF.

CE Low to High Transition

When the last data bit has been shifted into the CA3282,

the CE pin should be pulled high. At the rising edge of CE,

shift register data is latched into the output latch and the

outputs are activated with the new data. An internal 150

µs

delay timer will start at this rising edge to compensate for

high inrush currents in lamps and inductive loads. During

this period, the outputs will be protected only by the analog

current limiting circuits since resetting of the output latches

by fault conditions will be inhibited during this time. This

allows the device to handle inrush currents immediately

after turn on. When the 150

µs delay has elapsed, the out-

put voltages are sensed by the comparators and any out of

saturation outputs are latched off. The serial clock input pin

(SCK) should be low during CE transitions to avoid false

clocking of the shift register. The SCK input is gated by CE

so that the SCK input is ignored when CE is high.

Detecting Fault Conditions

Fault conditions may be checked as follows. Clock in a new

control byte and wait approximately 150

µs to allow the out-

puts to settle. Clock in the same control byte and note the

diagnostic data output at the MISO pin. The diagnostic bits

should be identical to the data clocked in. Any differences

will indicate a fault in the corresponding outputs. For exam-

ple, if an output was programmed ON by clocking in a zero,

and the corresponding diagnostic bit for that output is a

one, indicating the driver output is still high, then a short

circuit or overload condition may have caused the output to

unlatch. Alternatively, if the output was programmed OFF

by clocking in one, and the diagnostic bit for that output

shows a zero, then the probable cause is an open circuit

resulting in a floating output.

Dissipation In Multiple Outputs

The CA3282 Octal Power Driver has multiple MOS Output

Drivers and requires special consideration with regard to

maximum current and dissipation ratings. While each output

has a maximum current specification consistent with the

device structure, all such devices on the chip can not be

simultaneously rated to the same high level of peak current.

The total combined current and the dissipation on the chip

must be adjusted for maximum allowable ratings, given

simultaneous multiple output conditions.

1.5

1.0

0.5

0

0.2

0.4

0.6

0.8

CHARACTERISTICS OF CURRENT OUT vs

1.5

1.0

0.5

0

TYP CURRENT LIMITING

0

0.5

1.0

1.5

CHARACTERISTICS OF CURRENT OUT vs

CA3282